P

Inventor

NEIGER GILBERT

US263 patents
⚠️ This page may combine multiple inventors who share the name “NEIGER GILBERT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

41 patents
US7191440B2Mar 13, 2007

Tracking operating system process and thread execution and virtual machine execution in hardware or in a virtual machine monitor

INTEL CORP162 citations99
US6907600B2Jun 14, 2005

Virtual translation lookaside buffer

INTEL CORP215 citations99
US6678825B1Jan 13, 2004

Controlling access to multiple isolated memories in an isolated execution environment

INTEL CORP177 citations99
US6633963B1Oct 14, 2003

Controlling access to multiple memory zones in an isolated execution environment

INTEL CORP220 citations99
US6507904B1Jan 14, 2003

Executing isolated mode instructions in a secure system running in privilege rings

INTEL CORP289 citations99
US7757231B2Jul 13, 2010

System and method to deprivilege components of a virtual machine monitor

INTEL CORP79 citations98
US7225441B2May 29, 2007

Mechanism for providing power management through virtualization

INTEL CORP95 citations98
US7082615B1Jul 25, 2006

Protecting software environment in isolated execution

INTEL CORP78 citations98
US6996710B1Feb 7, 2006

Platform and method for issuing and certifying a hardware-protected attestation key

INTEL CORP74 citations98
US6760441B1Jul 6, 2004

Generating a key hieararchy for use in an isolated execution environment

INTEL CORP92 citations98
US7340582B2Mar 4, 2008

Fault processing for direct memory access address translation

INTEL CORP55 citations97
US7334107B2Feb 19, 2008

Caching support for direct memory access address translation

INTEL CORP74 citations97
US7296267B2Nov 13, 2007

System and method for binding virtual machines to hardware contexts

INTEL CORP94 citations97
US7222203B2May 22, 2007

Interrupt redirection for virtual partitioning

INTEL CORP73 citations97
US7562179B2Jul 14, 2009

Maintaining processor resources during architectural events

INTEL CORP30 citations96
US7272831B2Sep 18, 2007

Method and apparatus for constructing host processor soft devices independent of the host processor operating system

INTEL CORP57 citations96
US7035963B2Apr 25, 2006

Method for resolving address space conflicts between a virtual machine monitor and a guest operating system

INTEL CORP55 citations96
US7013484B1Mar 14, 2006

Managing a secure environment using a chipset in isolated execution mode

INTEL CORP62 citations96
US6990579B1Jan 24, 2006

Platform and method for remote attestation of a platform

INTEL CORP60 citations96
US6795905B1Sep 21, 2004

Controlling accesses to isolated memory using a memory controller for isolated execution

INTEL CORP58 citations96
US7555628B2Jun 30, 2009

Synchronizing a translation lookaside buffer to an extended paging table

INTEL CORP46 citations95
US7024555B2Apr 4, 2006

Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment

INTEL CORP50 citations95
US11416624B2Aug 16, 2022

Cryptographic computing using encrypted base addresses and used in multi-tenant environments

INTEL CORP11 citations94
US10558588B2Feb 11, 2020

Processors, methods, systems, and instructions to support live migration of protected containers

INTEL CORP15 citations94
US10303899B2May 28, 2019

Secure public cloud with protected guest-verified host control

INTEL CORP29 citations94
US9710401B2Jul 18, 2017

Processors, methods, systems, and instructions to support live migration of protected containers

INTEL CORP29 citations94
US10860709B2Dec 8, 2020

Encoded inline capabilities

INTEL CORP25 citations93
US9335943B2May 10, 2016

Method and apparatus for fine grain memory protection

INTEL CORP21 citations93
US7302511B2Nov 27, 2007

Chipset support for managing hardware interrupts in a virtual machine system

INTEL CORP27 citations93
US7254707B2Aug 7, 2007

Platform and method for remote attestation of a platform

INTEL CORP20 citations93
US7237051B2Jun 26, 2007

Mechanism to control hardware interrupt acknowledgement in a virtual machine system

INTEL CORP30 citations93
US7194634B2Mar 20, 2007

Attestation key memory device and bus

INTEL CORP27 citations93
US7177967B2Feb 13, 2007

Chipset support for managing hardware interrupts in a virtual machine system

INTEL CORP30 citations93
US7096497B2Aug 22, 2006

File checking using remote signing authority via a network

INTEL CORP32 citations93
US7085935B1Aug 1, 2006

Managing a secure environment using a chipset in isolated execution mode

INTEL CORP22 citations93
US7073071B1Jul 4, 2006

Platform and method for generating and utilizing a protected audit log

INTEL CORP19 citations93
US7013481B1Mar 14, 2006

Attestation key memory device and bus

INTEL CORP44 citations93
US6934817B2Aug 23, 2005

Controlling access to multiple memory zones in an isolated execution environment

INTEL CORP44 citations93
US6754815B1Jun 22, 2004

Method and system for scrubbing an isolated area of memory after reset of a processor operating in isolated execution mode if a cleanup flag is set

INTEL CORP50 citations93
US9858167B2Jan 2, 2018

Monitoring the operation of a processor

INTEL CORP16 citations92
US9116869B2Aug 25, 2015

Posting interrupts to virtual processors

INTEL CORP21 citations92

BENNETT STEVEN M

5 patents

NEIGER GILBERT

2 patents

MCKEEN FRANCIS X

1 patent

HUGHES CHRISTOPHER J

1 patent

Showing the top 50 of 263 patents by PatentIndex Score.