Inventor

YANG YAO-JEN

TW52 patents

Patents

50 patents

US11532752B2Dec 20, 2022

One-time-programmable memory devices having first transistor, second transistor, and resistor in series

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52

US12193223B2Jan 7, 2025

Memory device with improved anti-fuse read current

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52

US10878929B2Dec 29, 2020

eFuse circuit, method, layout, and structure

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52

Showing the top 50 of 52 patents by PatentIndex Score.

YANG YAO-JEN

Patents

Non-volatile memory device with reduced area

One-time programmable memory bit cell

Non-volatile memory device with reduced area

Reduced area efuse cell structure

Memory device, integrated circuit device and method

Semiconductor device including anti-fuse cell structure

Integrated circuit layout, structure, system, and methods

EFuse

Layout structure of memory array

One-time programmable memory bit cell

Memory circuit including a first program device

Reduced area eFuse cell structure

Memory device with improved anti-fuse read current

Non-volatile memory device with reduced area

Layout structures of memory array and related methods

Layout structures of memory array

Semiconductor device and method for manufacturing the same

Semiconductor memory devices with backside heater structure

Memory device and methods

Modified fuse structure and method of use

Method of manufacturing semiconductor device

Semiconductor device

Anti-fuse device and method

Efuse with fuse walls and method of manufacturing the same

Electrical fuse bit cell in integrated circuit having backside conducting lines

Anti-fuse array

Integrated circuit device

EFuse structure and method

Bit cell with back-side metal line device and method

Modified fuse structure and method of use

Electrical fuse bit cell in integrated circuit having backside conducting lines

One-time programmable memory bit cell

Method of and system for manufacturing semiconductor device

E-fuse

Integrated circuit structure

EFuse circuit, method, layout, and structure

Semiconductor device including anti-fuse cell

Integrated circuit including eFuse cell

Anti-fuse device method and layout

Efuse circuit, method, layout, and structure

Anti-fuse device, circuit, methods, and layout

Layout structure including anti-fuse cell

Layout structure including anti-fuse cell

Layout structure including anti-fuse cell

Integrated circuit and method of forming the same

Memory device and manufacturing method and test method of the same

Metal fuse structure by via landing

One-time-programmable memory devices having first transistor, second transistor, and resistor in series

Memory device with improved anti-fuse read current

eFuse circuit, method, layout, and structure