Inventor

RODGERS DION

US51 patents

⚠️ This page may combine multiple inventors who share the name “RODGERS DION”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RODGERS DION

INTEL CORP

Method and apparatus for entering and exiting multiple threads within a multithreaded processor

Method and apparatus for pausing execution in a processor or the like

Method and apparatus for processing an event occurrence within a multithreaded processor

Method and apparatus for suspending execution of a thread until a specified memory access occurs

Coherency techniques for suspending execution of a thread until a specified memory access occurs

Method and apparatus for processing an event occurrence for a least one thread within a multithreaded processor

Method and apparatus for disabling a clock signal within a multithreaded processor

Method and apparatus for disabling a clock signal within a multithreaded processor

Synchronizing a translation lookaside buffer to an extended paging table

Extended paging tables to map guest physical memory addresses from virtual memory page tables to host physical memory addresses in a virtual machine system

Transitioning between virtual machine monitor domains in a virtual machine environment

Support for nested fault in a virtual machine environment

Virtualizing memory type

System and method for controlling switching between VMM and VM using enabling value of VMM timer indicator and VMM timer value having a specified time

Alteration of functional unit partitioning scheme in multithreaded processor based upon thread statuses

Methods and systems to control virtual machines

Synchronizing a translation lookaside buffer with an extended paging table

Method and apparatus for processing an event occurrence within a multithreaded processor

Method and apparatus to provide secure application execution

Synchronizing a translation lookaside buffer with an extended paging table

Virtualization event processing in a layered virtualization architecture

User opt-in processor feature control capability

Method and apparatus for pausing execution in a processor or the like

Method and apparatus to provide secure application execution

Instruction set architecture-based inter-sequencer communications with a heterogeneous resource

Performing repeat string operations

Virtualization event processing in a layered virtualization architecture

Virtualization event processing in a layered virtualization architecture

Instruction set architecture-based inter-sequencer communications with a heterogeneous resource

Virtualization event processing in a layered virtualization architecture

System to profile and optimize user software in a managed run-time environment

BENNETT STEVEN M

Virtualization event processing in a layered virtualization architecture

Synchronizing a translation lookaside buffer with an extended paging table

Virtualizing physical memory in a virtual machine system utilizing multilevel translation table base registers to map guest virtual addresses to guest physical addresses then to host physical addresses

Translating a guest virtual address to a host physical address as guest software executes on a virtual machine

Injecting virtualization events in a layered virtualization architecture

Interrupt processing in a layered virtualization architecture

Synchronizing a translation lookaside buffer with an extended paging table

Virtual interrupt processing in a layered virtualization architecture

Virtualization event processing in a layered virtualization architecture

Virtualization event processing in a layered virtualization architecuture

Controlling virtual machines based on activity state

NEWBURN CHRIS J

System to profile and optimize user software in a managed run-time environment

Technique for context state management to reduce save and restore operations between a memory and a processor using in-use vectors

System to profile and optimize user software in a managed run-time environment

MCKEEN FRANCIS X

Method and apparatus to provide secure application execution

NEIGER GILBERT

Method and apparatus for a guest to access a privileged register

VAN DYKE DON A

Context state management for processor feature sets

WANG HONG

Instruction set architecture-based inter-sequencer communications with a heterogeneous resource

VAN DYKE DON

Context state management for processor feature sets