Inventor

SANKARAN RAJESH M

US97 patents

⚠️ This page may combine multiple inventors who share the name “SANKARAN RAJESH M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SANKARAN RAJESH M

INTEL CORP

Apparatus and method for memory management in a graphics processing environment

Posted interrupt architecture

Techniques for managing access to hardware accelerator memory

Systems, methods, and apparatuses for heterogeneous computing

Memory enclaves using process address space identifiers in a scalable input/output (I/O) virtualization (S-IOV) architecture

System, apparatus and method for page granular, software controlled multiple key memory encryption

Restricted address translation to protect against device-TLB vulnerabilities

Delivering interrupts to user-level applications

Systems, methods, and apparatuses for heterogeneous computing

Systems, methods, and apparatuses for heterogeneous computing

Network interface for data transport in heterogeneous computing environments

Hardware apparatuses and methods for distributed durable and atomic transactions in non-volatile memory

Method and apparatus for cache line write back operation

Synchronizing a translation lookaside buffer with an extended paging table

Apparatus and method for memory management in a graphics processing environment

Delivering interrupts to user-level applications

Apparatus and method for memory management in a graphics processing environment

Application driven hardware cache management

Delivering interrupts to user-level applications

Address translation for scalable virtualization of input/output devices

Processors, methods, systems, and instructions to selectively fence only persistent storage of given data relative to subsequent stores

High performance persistent memory for region-centric consistent and atomic updates

Accelerating boot time zeroing of memory based on non-volatile memory (NVM) technology

Method and apparatus for store durability and ordering in a persistent memory architecture

Systems, methods, and apparatuses for heterogeneous computing

Failover of virtual devices in a scalable input/output (I/O) virtualization (S-IOV) architecture

Non-posted write transactions for a computer bus

Flexible memory mapped input/output (I/O) space definition for a virtual device in a scalable I/O virtualization (S-IOV) architecture

Extending a root complex to encompass an external component

Address translation for scalable linked devices

Memory protection at a thread level for a memory protection key architecture

Aperture access processors, methods, systems, and instructions

Delivering interrupts to user-level applications

Virtualization of process address space identifiers for scalable virtualization of input/output devices

Aperture access processors, methods, systems, and instructions

Virtualization of process address space identifiers for scalable virtualization of input/output devices

Synchronizing a translation lookaside buffer with an extended paging table

Synchronizing a translation lookaside buffer with an extended paging table

Synchronizing a translation lookaside buffer with an extended paging table

Synchronizing a translation lookaside buffer with an extended paging table

Synchronizing a translation lookaside buffer with an extended paging table

Synchronizing a translation lookaside buffer with an extended paging table

Synchronizing a translation lookaside buffer with an extended paging table

Synchronizing a translation lookaside buffer with an extended paging table

SANKARAN RAJESH M

Virtual processor direct interrupt delivery mechanism

Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory

KUMAR SANJAY

Instruction and logic for flush-on-fail operation

NEIGER GILBERT

Virtualizing interrupt priority and delivery

COORAY NIRANJAN L

Apparatus and method for memory management in a graphics processing environment

BENNETT STEVEN M

Synchronizing a translation lookaside buffer with an extended paging table