Inventor
SCHOENBERG SEBASTIAN
US44 patents
⚠️ This page may combine multiple inventors who share the name “SCHOENBERG SEBASTIAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
34 patentsUS7191440B2Mar 13, 2007
Tracking operating system process and thread execution and virtual machine execution in hardware or in a virtual machine monitor
INTEL CORP162 citations99
US6907600B2Jun 14, 2005
Virtual translation lookaside buffer
INTEL CORP215 citations99
US7757231B2Jul 13, 2010
System and method to deprivilege components of a virtual machine monitor
INTEL CORP79 citations98
US7225441B2May 29, 2007
Mechanism for providing power management through virtualization
INTEL CORP95 citations98
US7035963B2Apr 25, 2006
Method for resolving address space conflicts between a virtual machine monitor and a guest operating system
INTEL CORP55 citations96
US7555628B2Jun 30, 2009
Synchronizing a translation lookaside buffer to an extended paging table
INTEL CORP46 citations95
US7020738B2Mar 28, 2006
Method for resolving address space conflicts between a virtual machine monitor and a guest operating system
INTEL CORP24 citations91
US8370559B2Feb 5, 2013
Executing a protected device model in a virtual machine
INTEL CORP10 citations84
US7886293B2Feb 8, 2011
Optimizing system behavior in a virtual machine environment
INTEL CORP14 citations84
US7840962B2Nov 23, 2010
System and method for controlling switching between VMM and VM using enabling value of VMM timer indicator and VMM timer value having a specified time
INTEL CORP16 citations84
US7840964B2Nov 23, 2010
Mechanism to transition control between components in a virtual machine environment
INTEL CORP16 citations84
US7313669B2Dec 25, 2007
Virtual translation lookaside buffer
INTEL CORP13 citations84
US8949571B2Feb 3, 2015
Synchronizing a translation lookaside buffer with an extended paging table
INTEL CORP2 citations74
US11381636B2Jul 5, 2022
Network function execution in information centric networks
INTEL CORP2 citations73
US10848584B2Nov 24, 2020
Routing in an information-centric network
INTEL CORP1 citations73
US10785341B2Sep 22, 2020
Processing and caching in an information-centric network
INTEL CORP1 citations72
US10747682B2Aug 18, 2020
Synchronizing a translation lookaside buffer with an extended paging table
INTEL CORP0 citations63
US10180911B2Jan 15, 2019
Synchronizing a translation lookaside buffer with an extended paging table
INTEL CORP0 citations63
US9678890B2Jun 13, 2017
Synchronizing a translation lookaside buffer with an extended paging table
INTEL CORP0 citations63
US9372806B2Jun 21, 2016
Synchronizing a translation lookaside buffer with an extended paging table
INTEL CORP0 citations63
US9372807B2Jun 21, 2016
Synchronizing a translation lookaside buffer with an extended paging table
INTEL CORP1 citations63
US9330021B2May 3, 2016
Synchronizing a translation lookaside buffer with an extended paging table
INTEL CORP0 citations63
US9298641B2Mar 29, 2016
Synchronizing a translation lookaside buffer with an extended paging table
INTEL CORP0 citations63
US9298640B2Mar 29, 2016
Synchronizing a translation lookaside buffer with an extended paging table
INTEL CORP0 citations63
US9262338B1Feb 16, 2016
Synchronizing a translation lookaside buffer with an extended paging table
INTEL CORP0 citations63
US9251094B2Feb 2, 2016
Synchronizing a translation lookaside buffer with an extended paging table
INTEL CORP0 citations63
US9141555B2Sep 22, 2015
Synchronizing a translation lookaside buffer with an extended paging table
INTEL CORP0 citations63
US9122624B2Sep 1, 2015
Synchronizing a translation lookaside buffer with an extended paging table
INTEL CORP0 citations63
US11316946B2Apr 26, 2022
Processing and caching in an information-centric network
INTEL CORP0 citations62
US10834223B2Nov 10, 2020
Hybrid information-centric and host-oriented networks
INTEL CORP0 citations52
US9442868B2Sep 13, 2016
Delivering interrupts directly to a virtual processor
INTEL CORP0 citations52
US7506121B2Mar 17, 2009
Method and apparatus for a guest to access a memory mapped device
INTEL CORP0 citations52
US11218907B2Jan 4, 2022
Publisher control in an information centric network
INTEL CORP0 citations51
US10223149B2Mar 5, 2019
Implementing device models for virtual machines with reconfigurable hardware
INTEL CORP0 citations42
BENNETT STEVEN M
3 patentsUS8099581B2Jan 17, 2012
Synchronizing a translation lookaside buffer with an extended paging table
BENNETT STEVEN M43 citations96
US8601233B2Dec 3, 2013
Synchronizing a translation lookaside buffer with an extended paging table
BENNETT STEVEN M2 citations73
US8296546B2Oct 23, 2012
Synchronizing a translation lookaside buffer with an extended paging table
BENNETT STEVEN M0 citations63