Inventor

ABADEER WAGDI W

US71 patents

⚠️ This page may combine multiple inventors who share the name “ABADEER WAGDI W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ABADEER WAGDI W

IBM

Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures

Concurrent Fin-FET and thick-body device fabrication

Low voltage programmable storage element

Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures

Method and structure to process thick and thin fins and variable fin to fin spacing

High voltage N-LDMOS transistors having shallow trench isolation region

Method and structure to process thick and thin fins and variable fin to fin spacing

Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure

Low voltage programmable storage element

Integrated antifuse structure for FINFET and CMOS devices

Semiconductor wafer processing method that allows device regions to be selectively annealed following back end of the line (BEOL) metal wiring layer formation

Structure for power-efficient cache memory

Programmable capacitors and methods of using the same

Method of forming high voltage N-LDMOS transistors having shallow trench isolation region with drain extensions

Voltage divider for integrated circuits

Electronically programmable antifuse and circuits made therewith

Method and system for testing the reliability of gate dielectric films

On-chip automatic system for impedance matching in very high speed input-output chip interfacing

Method of determining dielectric time-to-breakdown

Field effect transistor with air gap dielectric

Semiconductor structure and system for fabricating an integrated circuit chip

Voltage detection circuit and circuit for generating a trigger flag signal

MOSFET with decoupled halo before extension

Method and circuit for compensating for tunneling current

Method and apparatus for protecting circuits subjected to high voltage

Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same

Voltage reference circuit for low voltage applications in an integrated circuit

MOSFET with decoupled halo before extension

Termination resistance independent system for impedance matching in high speed input-output chip interfacing

Termination impedance independent system for impedance matching in high speed input-output chip interfacing

Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure

Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure

High-voltage SOI MOS device structure and method of fabrication

Back-end-of-line resistive semiconductor structures

Structure for a voltage detection circuit in an integrated circuit and method of generating a trigger flag signal

Threshold voltage compensation for pixel design of CMOS image sensors

CMOS image sensor having a third FET device with the gate terminal coupled to the diffusion region of a first FET device, the second terminal coupled to a column signal line, and the first terminal coupled to a row select signal

Device structures for active devices fabricated using a semiconductor-on-insulator substrate and design structures for a radiofrequency integrated circuit

CMOS imaging sensor having a third FET device with a gate terminal coupled to a second diffusion region of a first FET device and a first terminal coupled to a row select signal

Electronically programmable antifuse and circuits made therewith

Design structure for an automatic driver/transmission line/receiver impedance matching circuitry

Memory elements and methods of using the same

Design structure for a current control mechanism for power networks and dynamic logic keeper circuits

SRAM cell using tunnel current loading devices

Electronically programmable antifuse and circuits made therewith

Integrated circuit amplifier device and method using FET tunneling gate current

Digital to analog converter using tunneling current element

ABADEER WAGDI W

Field effect transistor with air gap dielectric

Forming an extremely thin semiconductor-on-insulator (ETSOI) layer

KAMAL LILIAN

Structure, design structure and process for increasing magnitude of device threshold voltage for low power applications