Inventor

CHATTY KIRAN V

US49 patents

⚠️ This page may combine multiple inventors who share the name “CHATTY KIRAN V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHATTY KIRAN V

IBM

Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures

Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures

Method and structure to process thick and thin fins and variable fin to fin spacing

Method and structure to process thick and thin fins and variable fin to fin spacing

Integrated antifuse structure for FINFET and CMOS devices

High voltage ESD power clamp

Field effect transistor with air gap dielectric

Method for creating a self-aligned SOI diode by removing a polysilicon gate during processing

Low trigger voltage, low leakage ESD NFET

MOSFET with decoupled halo before extension

Electrostatic discharge (ESD) device and method of fabricating

Low leakage electrostatic discharge protection circuit

MOSFET with decoupled halo before extension

SCR/MOS clamp for ESD protection of integrated circuits

Low trigger voltage electrostatic discharge NFET in triple well CMOS technology

High-voltage SOI MOS device structure and method of fabrication

Back-end-of-line resistive semiconductor structures

Enhanced stress-retention silicon-on-insulator devices and methods of fabricating enhanced stress retention silicon-on-insulator devices

Device structures for active devices fabricated using a semiconductor-on-insulator substrate and design structures for a radiofrequency integrated circuit

High voltage ESD power clamp

Integrated circuit amplifier device and method using FET tunneling gate current

Mixed voltage tolerant input/output electrostatic discharge devices

Silicon controlled rectifiers (SCR), methods of manufacture and design structures

Silicon controlled rectifier structure with improved junction breakdown and leakage control

Methods for forming back-end-of-line resistive semiconductor structures

On demand circuit function execution employing optical sensing

Device structures for a memory cell of a non-volatile random access memory and design structures for a non-volatile random access memory

Methods for fabricating active devices on a semiconductor-on-insulator substrate utilizing multiple depth shallow trench isolations

Methods of fabricating a device structure for use as a memory cell in a non-volatile random access memory

On demand circuit function execution employing optical sensing

Electrical overstress protection circuit

Mixed voltage tolerant electrostatic discharge protection silicon controlled rectifier with enhanced turn-on time

CAMPI JR JOHN B

Robust ESD protection circuit, method and design structure for tolerant and failsafe designs

Vertical NPNP structure in a triple well CMOS process

ESD field-effect transistor and integrated diffusion resistor

Silicon controlled rectifier based electrostatic discharge protection circuit with integrated JFETs, method of operation and design structure

CHANG SHUNHUA T

Signal and power supply integrated ESD protection device

Electrostatic discharge power clamp with a JFET based RC trigger circuit

ABADEER WAGDI W

Field effect transistor with air gap dielectric

Forming an extremely thin semiconductor-on-insulator (ETSOI) layer

ABOU-KHALIL MICHEL J

Low leakage, low capacitance electrostatic discharge (ESD) silicon controlled recitifer (SCR), methods of manufacture and design structure

Silicon controlled rectifiers (SCR), methods of manufacture and design structures

CHATTY KIRAN V

Silicon controlled rectifier structure with improved junction breakdown and leakage control

Enhanced stress-retention fin-FET devices and methods of fabricating enhanced stress retention fin-FET devices

INFINEON TECHNOLOGIES AG

ESD protection device and method

CHANG SHUNHUA

Electrostatic discharge (ESD) device and method of fabricating

CAMPI JOHN B

Vertical NPNP structure in a triple well CMOS process

GLOBALFOUNDRIES INC

Extremely thin semiconductor-on-insulator (ETSOI) layer

ABADEER WAGDI

Method of generating uniformly aligned well and isolation regions in a substrate and resulting structure