Inventor

GAUTHIER JR ROBERT J

US253 patents

⚠️ This page may combine multiple inventors who share the name “GAUTHIER JR ROBERT J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GAUTHIER JR ROBERT J

IBM

Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures

Design structures for high-voltage integrated circuits

Concurrent Fin-FET and thick-body device fabrication

Method of forming a semiconductor diode with depleted polysilicon gate structure

Gate-all-around fin device

Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures

Method and structure to process thick and thin fins and variable fin to fin spacing

High voltage N-LDMOS transistors having shallow trench isolation region

Thermal conductivity enhanced semiconductor structures and fabrication processes

Depleted polysilicon circuit element and method for producing the same

Semiconductor diode with depleted polysilicon gate structure and method

Gate-all-around fin device

Gate-all-around fin device

Gate-all-around fin device

Grounded body SOI SRAM cell

Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure

Method and structures for dual depth oxygen layers in silicon-on-insulator processes

Structure and method for improved latch-up using dual depth STI with impurity implant

Semiconductor structure having heterogeneous silicide regions and method for forming same

Structure for improved latch-up using dual depth STI with impurity implant

Series-connected nanowire structures

Gate-all-around fin device

Gate-all-around fin device

Gate-all-around fin device

Gate-all-around fin device

Gate-all-around fin device

Gate-all-around fin device

Structure and method for an electrostatic discharge (ESD) silicon controlled rectifier (SCR) structure

Stacked power clamp having a BigFET gate pull-up circuit

Method of forming high voltage N-LDMOS transistors having shallow trench isolation region with drain extensions

Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures

ESD protection power clamp for suppressing ESD events occurring on power supply terminals

Asymmetrical semiconductor device for ESD protection

Semiconductor structure having heterogenous silicide regions having titanium and molybdenum

Conductive coupling of electrical structures to a semiconductor device located under a buried oxide layer

Method for producing a polysilicon circuit element

Asymmetrical semiconductor device for ESD protection

Thermal conductivity enhanced semiconductor structures and fabrication processes

SOI MOSFET body contact and method of fabrication

Method of fabricating MOSFET with lateral resistor with ballasting

Method and apparatus for providing electrostatic discharge protection

Method of making a depleted poly-silicon edged MOSFET structure

Overvoltage and electrostatic discharge protection for a receiver circuit

Depleted poly-silicon edged MOSFET structure and method

High voltage ESD power clamp

Electro-static discharge protection circuit

Body contact MOSFET

Method and structures for dual depth oxygen layers in silicon-on-insulator processes

Body contact MOSFET

ABOU-KHALIL MICHEL J

Metal-insulator-metal capacitors with high capacitance density