Inventor

RANKIN JED H

US191 patents

⚠️ This page may combine multiple inventors who share the name “RANKIN JED H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RANKIN JED H

IBM

Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures

Concurrent Fin-FET and thick-body device fabrication

Planar substrate devices integrated with finfets and method of manufacture

Fin field effect transistor with self-aligned gate

Double planar gated SOI MOSFET structure

Double gate trench transistor

Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures

Method and structure to process thick and thin fins and variable fin to fin spacing

Circuit layout methodology using a shape processing application

High voltage N-LDMOS transistors having shallow trench isolation region

Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same

Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same

Self-aligned non-volatile random access memory cell and process to make the same

Vertical trench-formed dual-gate FET device structure and method for creation

Method and structure to process thick and thin fins and variable fin to fin spacing

Implanted asymmetric doped polysilicon gate FinFET

Double planar gated SOI MOSFET structure

Grounded body SOI SRAM cell

Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure

Method to define and tailor process limited lithographic features using a modified hard mask process

Polysilicon capacitor having large capacitance and low resistance and process for forming the capacitor

Integrated antifuse structure for FINFET and CMOS devices

Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the same

Hot-electron programmable latch for integrated circuit fuse applications and method of programming therefor

Process for defining a pattern using an anti-reflective coating and structure therefor

Doped single crystal silicon silicided eFuse

Planar substrate devices integrated with FinFETs and method of manufacture

Method of forming high voltage N-LDMOS transistors having shallow trench isolation region with drain extensions

Method of fabricating semiconductor side wall fin

Method and structure to create multiple device widths in FinFET technology in both bulk and SOI

Implanted asymmetric doped polysilicon gate FinFET

Method of fabricating a finfet

Fin capacitor

Conductive coupling of electrical structures to a semiconductor device located under a buried oxide layer

Active well schemes for SOI technology

Method and structure for creating high density buried contact for use with SOI processes for high performance logic

Body contact MOSFET

Body contact MOSFET

High mobility transistors in SOI and method for forming

Light controlled silicon on insulator device

Dual level contacts and method for forming

Antifuse for use with low k dielectric foam insulators

Integrated circuit structure with bulk silicon FinFET and methods of forming

Vertical bend waveguide coupler for photonics applications

Interface device with integrated solar cell(S) for power collection

Method for forming and structure of a recessed source/drain strap for a MUGFET

ANDERSON BRENT A

Devices with gate-to-gate isolation structures and methods of manufacture

Simultaneous formation of FinFET and MUGFET

Structure, method and system for complementary strain fill for integrated circuit chips

Devices with gate-to-gate isolation structures and methods of manufacture