Inventor

TONTI WILLIAM R

US219 patents

⚠️ This page may combine multiple inventors who share the name “TONTI WILLIAM R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TONTI WILLIAM R

IBM

Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures

Concurrent Fin-FET and thick-body device fabrication

Low-K gate spacers by fluorine implantation

SOI hybrid structure with selective epitaxial growth of silicon

Shared body and diffusion contact structure and method for fabricating same

Through-chip conductors for low inductance chip-to-chip integration and off-chip connections

Rolling ball connector

Chip interconnection structure using stub terminals

Low voltage programmable storage element

Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures

Method and structure to process thick and thin fins and variable fin to fin spacing

High voltage N-LDMOS transistors having shallow trench isolation region

High impedance antifuse

SOI hybrid structure with selective epitaxial growth of silicon

Chip edge interconnect apparatus and method

SIO stacked DRAM logic

SOI stacked DRAM logic

Method for novel SOI DRAM BICMOS NPN

Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and application

Methods and apparatus for blowing and sensing antifuses

Thermal conductivity enhanced semiconductor structures and fabrication processes

Method and apparatus for increasing interchip communications rates

Structures for wafer level test and burn-in

Rolling ball connector

Method and apparatus for interconnecting multiple circuit chips

SOI/bulk hybrid substrate and method of forming the same

Method and structure to process thick and thin fins and variable fin to fin spacing

MOS antifuse with low post-program resistance

Word line driver for dynamic random access memories

Electronic fuse structure and method of manufacturing

Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure

Method and apparatus for semiconductor integrated circuit testing and burn-in

Structure and method for creating vertical capacitor and anti-fuse in DRAM process employing vertical array device cell complex

Deep slit isolation with controlled void

Apparatus and method for antifuse with electrostatic assist

Integrated circuit capacitor

Isolated well ESD device

Structures and methods of anti-fuse formation in SOI

Through-chip conductors for low inductance chip-to-chip integration and off-chip connections

High frequency valid data strobe

Shallow trench isolation method utilizing combination of spacer and fill

Very low power logic circuit family with enhanced noise immunity

SOI/bulk hybrid substrate and method of forming the same

Three device BICMOS gain cell

Method of manufacturing an integrated ULSI heatsink

Large value capacitor for SOI

Multi-level storage gain cell with stepline

Method of making large value capacitor for SOI

Integrated ULSI heatsink

SIEMENS AG

Reduced parasitic leakage in semiconductor devices