Inventor
SHI YUN
US80 patents
⚠️ This page may combine multiple inventors who share the name “SHI YUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
19 patentsUS7790524B2Sep 7, 2010
Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures
IBM248 citations99
US7790543B2Sep 7, 2010
Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures
IBM80 citations98
US9224858B1Dec 29, 2015
Lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a below source isolation region and a method of forming the LDMOSFET
IBM20 citations93
US7999320B2Aug 16, 2011
SOI radio frequency switch with enhanced signal fidelity and electrical isolation
IBM21 citations93
US10050115B2Aug 14, 2018
Tapered gate oxide in LDMOS devices
IBM11 citations84
US8349697B2Jan 8, 2013
Field effect transistor with air gap dielectric
IBM6 citations84
US7670889B2Mar 2, 2010
Structure and method for fabrication JFET in CMOS
IBM12 citations84
US7485965B2Feb 3, 2009
Through via in ultra high resistivity wafer and related methods
IBM10 citations84
US9337310B2May 10, 2016
Low leakage, high frequency devices
IBM5 citations73
US9236449B2Jan 12, 2016
High voltage laterally diffused metal oxide semiconductor
IBM3 citations73
US9059276B2Jun 16, 2015
High voltage laterally diffused metal oxide semiconductor
IBM3 citations63
US8981475B2Mar 17, 2015
Lateral diffusion metal oxide semiconductor (LDMOS)
IBM2 citations63
US8962402B1Feb 24, 2015
Lateral diffusion metal oxide semiconductor (LDMOS) device with tapered drift electrode
IBM3 citations63
US8350338B2Jan 8, 2013
Semiconductor device including high field regions and related method
IBM2 citations63
US8012814B2Sep 6, 2011
Method of forming a high performance fet and a high voltage fet on a SOI substrate
IBM2 citations63
US7939395B2May 10, 2011
High-voltage SOI MOS device structure and method of fabrication
IBM6 citations63
US7939911B2May 10, 2011
Back-end-of-line resistive semiconductor structures
IBM2 citations63
US7804119B2Sep 28, 2010
Device structures with a hyper-abrupt P-N junction, methods of forming a hyper-abrupt P-N junction, and design structures for an integrated circuit
IBM2 citations63
US8912597B2Dec 16, 2014
Semiconductor device including asymmetric lightly doped drain (LDD) region, related method and design structure
IBM2 citations62
SKYWORKS SOLUTIONS INC
6 patentsUS11862725B2Jan 2, 2024
Transistors with schottky barriers
SKYWORKS SOLUTIONS INC2 citations71
US11417762B2Aug 16, 2022
Switch with integrated Schottky barrier contact
SKYWORKS SOLUTIONS INC3 citations71
US11742408B2Aug 29, 2023
Cascode amplifier optimization
SKYWORKS SOLUTIONS INC0 citations62
US10886382B2Jan 5, 2021
Cascode amplifier optimization
SKYWORKS SOLUTIONS INC0 citations62
US12593491B2Mar 31, 2026
Semiconductor devices with Schottky barriers
SKYWORKS SOLUTIONS INC0 citations60
US11705487B2Jul 18, 2023
Transistors having reduced parasitics and enhanced performance
SKYWORKS SOLUTIONS INC0 citations60
BOTULA ALAN B
5 patentsUS8133774B2Mar 13, 2012
SOI radio frequency switch with enhanced electrical isolation
BOTULA ALAN B12 citations84
US8748285B2Jun 10, 2014
Noble gas implantation region in top silicon layer of semiconductor-on-insulator substrate
BOTULA ALAN B5 citations73
US8866226B2Oct 21, 2014
SOI radio frequency switch with enhanced electrical isolation
BOTULA ALAN B2 citations63
US8518782B2Aug 27, 2013
Semiconductor device including asymmetric lightly doped drain (LDD) region, related method and design structure
BOTULA ALAN B4 citations62
US8299561B2Oct 30, 2012
Shielding for high-voltage semiconductor-on-insulator devices
BOTULA ALAN B2 citations62
GOOGLE LLC
4 patentsGLOBALFOUNDRIES INC
3 patentsUS9786606B2Oct 10, 2017
Semiconductor structures with isolated ohmic trenches and stand-alone isolation trenches and related method
GLOBALFOUNDRIES INC9 citations82
US9799652B1Oct 24, 2017
Semiconductor structure with a dopant implant region having a linearly graded conductivity level and method of forming the structure
GLOBALFOUNDRIES INC3 citations73
US9768028B1Sep 19, 2017
Semiconductor structure with a dopant implant region having a linearly graded conductivity level and method of forming the structure
GLOBALFOUNDRIES INC2 citations73
BOEING CO
3 patentsCAMILLO-CASTILLO RENATA
2 patentsABOU-KHALIL MICHEL J
1 patentANDERSON FREDERICK G
1 patentABADEER WAGDI W
1 patentDING HANYI
1 patentATLAS COPCO AIRPOWER NV
1 patentCLARK JR WILLIAM F
1 patentJOHNSON JEFFREY B
1 patentHANGZHOU LIJIAN DIGITAL TECH CO LTD
1 patentShowing the top 50 of 80 patents by PatentIndex Score.