Inventor

GARNEY JOHN I

US65 patents

⚠️ This page may combine multiple inventors who share the name “GARNEY JOHN I”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GARNEY JOHN I

INTEL CORP

System for enabling access to device driver residing in resource memory corresponding to coupled resource by allowing memory mapping to device driver to be executed

System for copying device driver stub into allocated portion of system memory corresponding to receiving resource to enable device driver execution from resource memory

Preservation of a computer system processing state in a mass storage device

Device driver configuration in a computer system

Interface for a block addressable mass storage system

Storing dynamically loaded device drivers on a mass storage device to support access to removable computer cards

Extensible bios for boot support of devices on multiple hierarchical buses

Preventing storage of streaming accesses in a cache

Method and apparatus for implementing a wireless universal serial bus host controller by interfacing a universal serial bus hub as a universal serial bus device

Split Transaction protocol for a bus system

Transaction scheduling for a bus system

Method to reduce system bus load due to USB bandwidth reclamation

Method to reduce system bus load due to USB bandwidth reclamation

Split transaction protocol for a bus system

Using non-volatile memories for disk caching of partition table entries

Writing cache lines on a disk drive

Transaction scheduling for a bus system in a multiple speed environment

Generation of stereoscopic displays using image approximation

Mechanism supporting execute in place read only memory applications located on removable computer cards

Two-part memory card socket connector and related interrupt handler

Merging write-back and write-through cache policies

Apparatus and method for processing isochronous interrupts

Method for minimizing CPU memory latency while transferring streaming data

I/O peripheral device for use in a store-and-forward segment of a peripheral bus

Architecture for the isochronous transfer of information within a computer system

System boot time reduction method

Method and apparatus for lossless resume capability with peripheral devices

Half duplex link with isochronous and asynchronous arbitration

Nak throttling for USB host controllers

Apparatus and method to allow and synchronize schedule changes in a USB enhanced host controller

Method and apparatus for budget development under universal serial bus protocol in a multiple speed transmission environment

Method and system for scheduling transactions over a half duplex link

Method and apparatus for preservation of failure state in a read destructive memory

Dynamic master/slave configuration for multiple expansion modules

Transaction scheduling for a bus system in a multiple speed environment

Method and apparatus for improving time constraints and extending limited length cables in a multiple-speed bus

Method and apparatus for period promotion avoidance for hubs

Method and apparatus for isochronous data transport over an asynchronous bus

Memory cache management for isochronous memory access

Architecture providing isochronous access to memory in a system

System partitioning to present software as platform level functionality via inter-partition bridge including reversible mode logic to switch between initialization, configuration, and execution mode

Split transaction protocol for a bus system

Split transaction protocol for a bus system

Dynamic master/slave configuration for multiple expansion modules

Method and apparatus to store initialization and configuration information

Methods and apparatus for data transfer between partitions in a computer system

Write-back disk cache

Interacting with optional read-only memory

MOORE TERRILL M

Security arrangements for extended USB protocol stack of a USB host system

MCCI CORP

Security arrangements for extended USB protocol stack of a USB host system