Inventor
RICHTER DAVID E
US13 patents
⚠️ This page may combine multiple inventors who share the name “RICHTER DAVID E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
EXPONENTIAL TECHN INC
9 patentsUS5781750AJul 14, 1998
Dual-instruction-set architecture CPU with hidden software emulation mode
EXPONENTIAL TECHN INC209 citations99
US5781457AJul 14, 1998
Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU
EXPONENTIAL TECHN INC189 citations99
US5481693AJan 2, 1996
Shared register architecture for a dual-instruction-set CPU
EXPONENTIAL TECHN INC153 citations99
US5664159ASep 2, 1997
Method for emulating multiple debug breakpoints by page partitioning using a single breakpoint register
EXPONENTIAL TECHN INC106 citations98
US5481684AJan 2, 1996
Emulating operating system calls in an alternate instruction set using a modified code segment descriptor
EXPONENTIAL TECHN INC231 citations98
US5685009ANov 4, 1997
Shared floating-point registers and register port-pairing in a dual-architecture CPU
EXPONENTIAL TECHN INC113 citations96
US5652872AJul 29, 1997
Translator having segment bounds encoding for storage in a TLB
EXPONENTIAL TECHN INC81 citations96
US5598553AJan 28, 1997
Program watchpoint checking using paging with sub-page validity
EXPONENTIAL TECHN INC49 citations96
US5440710AAug 8, 1995
Emulation of segment bounds checking using paging with sub-page validity
EXPONENTIAL TECHN INC97 citations96
S3 INC
3 patentsUS5848264ADec 8, 1998
Debug and video queue for multi-processor chip
S3 INC204 citations98
US6076155AJun 13, 2000
Shared register architecture for a dual-instruction-set CPU to facilitate data exchange between the instruction sets
S3 INC73 citations96
US5805918ASep 8, 1998
Dual-instruction-set CPU having shared register for storing data before switching to the alternate instruction set
S3 INC41 citations92