Inventor

SAKAKIBARA KIYOHIKO

JP52 patents

⚠️ This page may combine multiple inventors who share the name “SAKAKIBARA KIYOHIKO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAKAKIBARA KIYOHIKO

SANDISK TECHNOLOGIES LLC

Three-dimensional memory device containing through-memory-level contact via structures

Three-dimensional memory device employing direct source contact and hole current detection and method of making the same

Three-dimensional memory device with self-aligned vertical conductive strips having a gate-all-around configuration and method of making the same

Three-dimensional memory device having nitrided direct source strap contacts and method of making thereof

Three-dimensional memory device containing a capped insulating source line core and method of making the same

Three-dimensional memory device having vertical semiconductor channels including source-side boron-doped pockets and methods of making the same

Three-dimensional memory device using a buried source line with a thin semiconductor oxide tunneling layer

Locally-trap-characteristic-enhanced charge trap layer for three-dimensional memory structures

Three-dimensional memory device containing a carbon-doped source contact layer and methods for making the same

Three-dimensional flat memory device including a dual dipole blocking dielectric layer and methods of making the same

Three-dimensional memory device and methods of making the same using replacement drain select gate electrodes

Three-dimensional memory device with straddling drain select electrode lines and method of making thereof

Three-dimensional junction memory device and method reading thereof using hole current detection

Buried source line structure for boosting read scheme

Three-dimensional memory device including bottle-shaped memory stack structures and drain-select gate electrodes having cylindrical portions

Three-dimensional memory device and methods of making the same using replacement drain select gate electrodes

Three-dimensional memory device containing vertically isolated charge storage regions and method of making thereof

Reverse VT-state operation and optimized BiCS device structure

Three-dimensional flat memory device including a dual dipole blocking dielectric layer and methods of making the same

Reverse VT-state operation and optimized BiCS device structure

Threshold voltage setting with boosting read scheme

Threshold voltage setting with boosting read scheme

Boosting read scheme with back-gate bias

Boosting read scheme with back-gate bias

Boosting read scheme with back-gate bias

MITSUBISHI ELECTRIC CORP

Non-volatile semiconductor memory and methods of driving, operating, and manufacturing this memory

Non-volatile semiconductor memory device

Solid-state imaging device with improved photodetector

Non-volatile semiconductor memory device

Semiconductor device having a solid-state image sensor

Nonvolatile semiconductor memory device and method of manufacturing the same

Nonvolatile semiconductor memory device having controlled charge pump load

Method of making solid-state imaging device

Nonvolatile semiconductor memory device capable of suppressing reduction of bit line potential in write-back operation and erase method

Semiconductor device with a plurality of semiconductor elements

Nonvolatile semiconductor memory device and method of manufacturing the same

Charge coupled device

Nonvolatile semiconductor memory device capable of suppressing reduction of bit line potential in write-back operation and erase method

Non-volatile semiconductor memory device and method for producing the same

Method of making a charge coupled device

SANDISK TECHNOLOGIES INC

Three-dimensional memory devices containing memory stack structures with position-independent threshold voltage

Mid-tunneling dielectric band gap modification for enhanced data retention in a three-dimensional semiconductor device

Epitaxial source region for uniform threshold voltage of vertical transistors in 3D memory devices

Three-dimensional P-I-N memory device and method reading thereof using hole current detection

Blocking oxide in memory opening integration scheme for three-dimensional memory structure

Method of reducing control gate electrode curvature in three-dimensional memory devices

RENESAS TECH CORP

Non-volatile semiconductor memory and methods of driving, operating, and manufacturing this memory

Non-volatile semiconductor memory device suppressing write-back fault

KASAOKA TATSUO

Method of manufacturing semiconductor device that uses both a normal photomask and a phase shift mask for defining interconnect patterns

SAKAKIBARA KIYOHIKO

Semiconductor device having differential pair transistors with a switchable tail current