Inventor

KLASS EDGARDO F

US52 patents

⚠️ This page may combine multiple inventors who share the name “KLASS EDGARDO F”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KLASS EDGARDO F

SUN MICROSYSTEMS INC

Edge-triggered staticized dynamic flip-flop with conditional shut-off mechanism

Edge-triggered staticized dynamic flip-flop with scan circuitry

Single phase edge-triggered dual-rail dynamic flip-flop

Method of implementing a scan flip-flop using an edge-triggered staticized dynamic flip-flop

Flip-flop with logic function incorporated therein with minimal time penalty

Single-phase edge-triggered dual-rail dynamic flip-flop

Apparatus and method for improving the noise immunity of a dynamic logic signal repeater

Two pole coupling noise analysis model for submicron integrated circuit design verification

Edge-triggered dual-rail dynamic flip-flop with self-shut-off mechanism

Active pulsed scheme for driving long interconnects

Edge-triggered dual-rail dynamic flip-flop with an enhanced self-shut-off mechanism

Clock skew tolerant clocking scheme

Non-blocking delayed clocking system for domino logic

Method for generating non-blocking delayed clocking signals for domino logic

Non-blocking multiple phase clocking scheme for dynamic logic

System and method for detecting and preventing race condition in circuits

Modified high speed flop design with self adjusting, data selective, evaluation window

Modified domino logic circuit with high input noise rejection

Clocked full-rail differential logic with sense amplifier and shut-off

Conditional precharge design in staticized dynamic flip-flop with clock enable

Method for clock control of clocked full-rail differential logic circuits with sense amplifier and shut-off

Clocked full-rail differential logic with shut-off

Method for increasing the power efficiency and noise immunity of clocked full-rail differential logic

APPLE INC

Scan latch with phase-free scan enable

Self-gating synchronizer

Low latency synchronizer circuit

Power saving with dual-rail supply voltage scheme

Clock gater with test features and low setup time

Method and software tool for analyzing and reducing the failure rate of an integrated circuit

Area-aware test pattern coverage optimization

Methods and systems for switchable logic to recover integrated circuits with short circuits

Lockup latch for subthreshold operation

Mechanism for measuring read current variability of SRAM cells

PA SEMI INC

Digital leakage detector that detects transistor leakage current in an integrated circuit

Combined multiplex or/flop

Pulsed flop with scan circuitry

Pulsed flop with embedded logic

Digital jitter detector

TANG BO

Scan latch with phase-free scan enable

Low latency synchronizer circuit

Self-gating synchronizer

JAIN ASHISH R

Apparatus and method for testing sense amplifier thresholds on an integrated circuit

Apparatus and method for testing driver writeability strength on an integrated circuit

Apparatus and method for testing driver writeability strength on an integrated circuit

(unassigned)

Method for implementing a single phase edge-triggered dual-rail dynamic flip-flop

LAU BETTY Y

IR(voltage) drop analysis in integrated circuit timing

CAMPBELL BRIAN J

Clock gater with test features and low setup time

OLIVA ANTONIETTA

Method and software tool for analyzing and reducing the failure rate of an integrated circuit

KLASS EDGARDO F

Pulse flop with enhanced scan implementation

SONI APURVA H

Versatile method and tool for simulation of aged transistors