Inventor

DORTU JEAN-MARC

DE22 patents

⚠️ This page may combine multiple inventors who share the name “DORTU JEAN-MARC”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DORTU JEAN-MARC

INFINEON TECHNOLOGIES AG

Printed circuit board for semiconductor memory device

Integrated memory having a memory cell array containing a plurality of memory banks, and circuit configuration having an integrated memory

Semiconductor memory device with write protected memory banks

Memory, processor system and method for performing write operations on a memory region

Integrated memory chip with a dynamic memory

Data output interface, in particular for semiconductor memories

Semiconductor memory system with a variable and settable preamble f

Semiconductor memory having a first and second sense amplifier for sensing a memory cell voltage during a normal mode and a refresh mode

Circuit configuration with signal lines for serially transmitting a plurality of bit groups

Memory apparatus having a short word line cycle time and method for operating a memory apparatus

Integrated dynamic memory device and method for operating an integrated dynamic memory

SIEMENS AG

Clock latency compensation circuit for DDR timing

Lock arrangement for a calibrated DLL in DDR SDRAM applications

Power amplifier circuit for integrated digital circuits

Address amplifier circuit having automatic interlock and protection against multiple addressing for use in static GaAs RAMs

INFINEON TECHNOLOGIES CORP

Frequency range trimming for a delay line

Delay element using a delay locked loop

Delay-locked-loop (DLL) having symmetrical rising and falling clock edge type delays

IBM

Variable domain redundancy replacement configuration for a memory device

Method of making a memory device fault tolerant using a variable domain redundancy replacement configuration

THOMSON CSF

Field effect transistor operating in the enhancement mode

DORTU JEAN-MARC

Semiconductor memory having a short effective word line cycle time and method for reading data from a semiconductor memory of this type