Inventor
BANERJEE KOUSHIK
US25 patents
⚠️ This page may combine multiple inventors who share the name “BANERJEE KOUSHIK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
21 patentsUS6440770B1Aug 27, 2002
Integrated circuit package
INTEL CORP46 citations94
US5557502ASep 17, 1996
Structure of a thermally and electrically enhanced plastic ball grid array package
INTEL CORP105 citations94
US7045890B2May 16, 2006
Heat spreader and stiffener having a stiffener extension
INTEL CORP35 citations92
US5734559AMar 31, 1998
Staggered bond finger design for fine pitch integrated circuit packages
INTEL CORP47 citations92
US5444602AAug 22, 1995
An electronic package that has a die coupled to a lead frame by a dielectric tape and a heat sink that providees both an electrical and a thermal path between the die and teh lead frame
INTEL CORP20 citations92
US6043559AMar 28, 2000
Integrated circuit package which contains two in plane voltage busses and a wrap around conductive strip that connects a bond finger to one of the busses
INTEL CORP20 citations91
US6031283AFeb 29, 2000
Integrated circuit package
INTEL CORP19 citations91
US5787575AAug 4, 1998
Method for plating a bond finger of an intergrated circuit package
INTEL CORP28 citations91
US5811880ASep 22, 1998
Design for mounting discrete components inside an integrated circuit package for frequency governing of microprocessors
INTEL CORP20 citations89
US10360977B2Jul 23, 2019
Tailoring current magnitude and duration during a programming pulse for a memory device
INTEL CORP2 citations73
US6214638B1Apr 10, 2001
Bond pad functional layout on die to improve package manufacturability and assembly
INTEL CORP11 citations73
US5895977AApr 20, 1999
Bond pad functional layout on die to improve package manufacturability and assembly
INTEL CORP12 citations73
US11100984B2Aug 24, 2021
Non volatile cross point memory having word line pass transistor with multiple active states
INTEL CORP0 citations62
US10884640B2Jan 5, 2021
Set technique for phase change memory
INTEL CORP1 citations62
US10796761B2Oct 6, 2020
Tailoring current magnitude and duration during a programming pulse for a memory device
INTEL CORP1 citations62
US10248351B1Apr 2, 2019
Set technique for phase change memory
INTEL CORP1 citations62
US6459563B1Oct 1, 2002
Method and apparatus for polygonal heat slug
INTEL CORP3 citations62
US6256189B1Jul 3, 2001
Heat slug design which facilitates mounting of discrete components on a package without losing lands or pins in the package
INTEL CORP2 citations62
US5345363ASep 6, 1994
Method and apparatus of coupling a die to a lead frame with a tape automated bonded tape that has openings which expose portions of the tape leads
INTEL CORP2 citations59
US10553286B2Feb 4, 2020
Tailoring timing offsets during a programming pulse for a memory device
INTEL CORP1 citations56
US6403891B1Jun 11, 2002
Metallization removal under the laser mark area for substrates
INTEL CORP3 citations54
MICRON TECHNOLOGY INC
4 patentsUS11170853B2Nov 9, 2021
Modified write voltage for memory devices
MICRON TECHNOLOGY INC2 citations71
US11705197B2Jul 18, 2023
Modified write voltage for memory devices
MICRON TECHNOLOGY INC0 citations61
US12040014B2Jul 16, 2024
Configurable resistivity for lines in a memory device
MICRON TECHNOLOGY INC0 citations57
US11495293B2Nov 8, 2022
Configurable resistivity for lines in a memory device
MICRON TECHNOLOGY INC0 citations57