Inventor
KOEHL JUERGEN
DE39 patents
⚠️ This page may combine multiple inventors who share the name “KOEHL JUERGEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
29 patentsUS7308669B2Dec 11, 2007
Use of redundant routes to increase the yield and reliability of a VLSI layout
IBM211 citations98
US6218631B1Apr 17, 2001
Structure for reducing cross-talk in VLSI circuits and method of making same using filled channels to minimize cross-talk
IBM88 citations97
US7145873B2Dec 5, 2006
Switching arrangement and method with separated output buffers
IBM25 citations92
US6237128B1May 22, 2001
Method and apparatus for enabling parallel layout checking of designing VLSI-chips
IBM22 citations89
US7865855B2Jan 4, 2011
Method and system for generating a layout for an integrated electronic circuit
IBM10 citations84
US7526743B2Apr 28, 2009
Method for routing data paths in a semiconductor chip with a plurality of layers
IBM9 citations84
US7386815B2Jun 10, 2008
Test yield estimate for semiconductor products created from a library
IBM9 citations83
US6904584B2Jun 7, 2005
Method and system for placing logic nodes based on an estimated wiring congestion
IBM14 citations79
US7844931B2Nov 30, 2010
Method and computer system for optimizing the signal time behavior of an electronic circuit design
IBM6 citations69
US7392497B2Jun 24, 2008
Regular routing for deep sub-micron chip design
IBM7 citations68
US7984394B2Jul 19, 2011
Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same
IBM3 citations63
US7962877B2Jun 14, 2011
Port assignment in hierarchical designs by abstracting macro logic
IBM4 citations63
US7960836B2Jun 14, 2011
Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same
IBM2 citations63
US7755408B2Jul 13, 2010
Redundancy in signal distribution trees
IBM4 citations63
US7487476B2Feb 3, 2009
Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool
IBM2 citations63
US7336115B2Feb 26, 2008
Redundancy in signal distribution trees
IBM3 citations63
US7289659B2Oct 30, 2007
Method and apparatus for manufacturing diamond shaped chips
IBM2 citations63
US8010925B2Aug 30, 2011
Method and system for placement of electric circuit components in integrated circuit design
IBM2 citations62
US7996808B2Aug 9, 2011
Computer readable medium, system and associated method for designing integrated circuits with loop insertions
IBM4 citations62
US8010916B2Aug 30, 2011
Test yield estimate for semiconductor products created from a library
IBM2 citations61
US8056037B2Nov 8, 2011
Method for validating logical function and timing behavior of a digital circuit decision
IBM2 citations60
US8015527B2Sep 6, 2011
Routing of wires of an electronic circuit
IBM5 citations60
US7206308B2Apr 17, 2007
Method of providing a non-blocking routing network
IBM4 citations60
US7886245B2Feb 8, 2011
Structure for optimizing the signal time behavior of an electronic circuit design
IBM4 citations58
US7961932B2Jun 14, 2011
Method and apparatus for manufacturing diamond shaped chips
IBM1 citations52
US7962881B2Jun 14, 2011
Via structure to improve routing of wires within an integrated circuit
IBM2 citations52
US7490310B2Feb 10, 2009
Method for creating a layout for an electronic circuit
IBM4 citations52
US9256430B2Feb 9, 2016
Instruction scheduling approach to improve processor performance
IBM0 citations49
US7398485B2Jul 8, 2008
Yield optimization in router for systematic defects
IBM0 citations41
KOEHL JUERGEN
2 patentsBICKFORD JEANNE P
2 patentsUS8418090B2Apr 9, 2013
Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool
BICKFORD JEANNE P0 citations52
US8132129B2Mar 6, 2012
Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool
BICKFORD JEANNE P0 citations52