Inventor

YAN HONGWEN

US39 patents

⚠️ This page may combine multiple inventors who share the name “YAN HONGWEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YAN HONGWEN

IBM

Method for reducing line edge roughness of oxide material using chemical oxide removal

Method to controllably form notched polysilicon gate structures

Hard mask process to prevent surface roughness for selective dielectric etching

Direct contact between high-κ/metal gate and wiring process flow

Advanced high-k gate stack patterning and structure containing a patterned high-k gate stack

CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials

Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFET

CMOS (complementary metal oxide semiconductor) devices having metal gate NFETs and poly-silicon gate PFETs

Method of forming gate stack and structure thereof

Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch

Etch selectivity enhancement for tunable etch resistant anti-reflective layer

Gate metal recess for oxidation protection and parasitic capacitance reduction

Plasma shallow doping and wet removal of depth control cap

Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes

Reduced dielectric constant spacer materials integration for high speed logic gates

Selective dry etch of a dielectric film

Microfabricated air bridges for quantum circuits

Residue free patterned layer formation method applicable to CMOS structures

Wiring structure for integrated circuit with reduced intralevel capacitance

Sacrificial material facilitating protection of a substrate in a qubit device

III-V extension by high temperature plasma doping

Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches

Method of patterning multilayer metal gate structures for CMOS devices

Apparatus and method for shielding a wafer from charged particles during plasma etching

Array and moat isolation structures and method of manufacture

CMOS (complementary metal oxide semiconductor) devices having metal gate NFETS and poly-silicon gate PFETS

Smooth metal layers in Josephson junction devices

Self-aligned trench metal-alloying for III-V nFETs

CHEN TZE-CHIANG

CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials

CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials

ZHANG YING

Method of removing high-K dielectric layer on sidewalls of gate structure

COOLBAUGH DOUGLAS D

Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor

CHUDZIK MICHAEL P

Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches

ADKISSON JAMES WILLIAM

Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes

TOKYO ELECTRON LTD

Plasma co-doping to reduce the forming voltage in resistive random access memory (ReRAM) devices

KHARE MUKESH V

Protecting exposed metal gate structures from etching processes in integrated circuit manufacturing

KUSABA NAOYOSHI

Array and moat isolation structures and method of manufacture

VEGA REINALDO A

Semiconductor structures with dual trench regions and methods of manufacturing the semiconductor structures

DALTON TIMOTHY J

Addition of ballast hydrocarbon gas to doped polysilicon etch masked by resist