Inventor

HU YONGZHONG

US26 patents

⚠️ This page may combine multiple inventors who share the name “HU YONGZHONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HU YONGZHONG

ALPHA & OMEGA SEMICONDUCTOR

One time programmable memory cell

Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process

Completely decoupled high voltage and low voltage transistor manufacturing processes

Top drain LDMOS

Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions

Device configuration of asymmetrical DMOSFET with schottky barrier source

One-time programmable (OTP) memory cell

ADVANCED MICRO DEVICES INC

Method for forming self-aligned contacts and local interconnects using self-aligned local interconnects

Method for forming self-aligned contacts and local interconnects using decoupled local interconnect process

Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer

In-situ process for fabricating a semiconductor device with integral removal of antireflection and etch stop layers

Method for using a low dielectric constant layer as a semiconductor anti-reflective coating

Method for eliminating anti-reflective coating in semiconductors

LATTICE SEMICONDUCTOR CORP

Single-poly two-transistor EEPROM cell with differentially doped floating gate

Compact single-poly two transistor EEPROM cell

EEPROM cell having a floating-gate transistor within a cell well and a process for fabricating the memory cell

Eeprom device with improved capacitive coupling and fabrication process

Flash technology transistors and methods for forming the same

HU YONGZHONG

Method of fabrication and device configuration of asymmetrical DMOSFET with schottky barrier source

Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process

Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions

Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions

TAI SUNG-SHAN

Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET

Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET

SEMICONDUCTOR COMPONENTS IND LLC

Integrated isolation capacitance structure

MALLIKARJUNASWAMY SHEKAR

Top drain LDMOS