Inventor

HASS DAVID T

US45 patents

⚠️ This page may combine multiple inventors who share the name “HASS DAVID T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HASS DAVID T

RMI CORP

Advanced processor with system on a chip interconnect technology

Advanced processor with cache coherency

Advanced processor with use of bridges on a data movement ring for optimal redirection of memory and I/O traffic

Advanced processor translation lookaside buffer management in a multithreaded system

Advanced processor translation lookaside buffer management in a multithreaded system

Advanced processor with implementation of memory ordering on a ring based data movement network

Advanced processor messaging apparatus including fast messaging ring components configured to accomodate point-to-point transfer of non-memory related messages

Advanced processor with scheme for optimal packet flow in a multi-processor system on a chip

System and method for deflate processing within a compression engine

Advanced processor system using request, data, snoop, and response rings

System and method for Huffman decoding within a compression engine

NETLOGIC MICROSYSTEMS INC

Advanced processor with mechanism for packet distribution at high line rate

System and method for offloading packet protocol encapsulation from software

Delegating network processor operations to star topology serial bus interfaces

Advanced processor scheduling in a multithreaded system

Advanced processor with mechanism for enforcing ordering between information sent on two independent networks

Method and apparatus for implementing cache coherency of a processor

Advanced processor with mechanism for fast packet queuing operations

Advanced processor translation lookaside buffer management in a multithreaded system

Messaging network for processing data using multiple processor cores

System and method for conditionally sending a request for data to a home node

HASS DAVID T

Advanced processor with mechanism for packet distribution at high line rate

Multi-core multi-threaded processing systems with instruction reordering in an in-order pipeline

Method and apparatus for implementing cache coherency of a processor

System and method for parsing and allocating a plurality of packets to processor core threads

Advanced processor translation lookaside buffer management in a multithreaded system

Advanced processor with fast messaging network technology

Processor with packet ordering device

GARG GAURAV

System and method for conditionally sending a request for data to a home node

System, method, and computer program product to distribute workload

System, method, and computer program product for conditionally sending a request for data to a node based on a determination

Advanced processor with credit based scheme for optimal packet flow in a multi-processor system on a chip

Network-on-chip system, method, and computer program product for transmitting messages utilizing a centralized on-chip shared memory switch

Performance of a stride-based prefetcher on an out-of-order processing unit (CPU)

KUILA KAUSHIK

Programmable micro-core processors for packet parsing

Programmable micro-core processors for packet parsing with packet ordering

System and method for offloading packet protocol encapsulation from software

ZHU JULIANNE J

Device configuration for multiprocessor systems

Multi-part clock management

RASHID ABBAS

Weighted instruction count scheduling

Advanced processor with interfacing messaging network to a CPU

ZHU JULIANNE JIANG

Delegating network processor operations to star topology serial bus interfaces

Delegating network processor operations to star topology serial bus interfaces

SHAHID AHMED

System and method for reducing latency associated with timestamps in a multi-core, multi-threaded processor

BROADCOM CORP

System, method, and computer program product for conditionally sending a request for data to a node based on a determination