Inventor

SULTAN AKIF

US31 patents

⚠️ This page may combine multiple inventors who share the name “SULTAN AKIF”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SULTAN AKIF

ADVANCED MICRO DEVICES INC

Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion

Advanced cobalt silicidation with in-situ hydrogen plasma clean

Method for improving MOS mobility

Hybrid silicon on insulator/bulk strained silicon technology

Source/drain formation with sub-amorphizing implantation

Formation of low resistance, ultra shallow LDD junctions employing a sub-surface, non-amorphous implant

Ultra-shallow p-type junction having reduced sheet resistance and method for producing shallow junctions

Fabrication process employing a single dopant implant for formation of a drain extension region and a drain region of an LDD MOSFET using enhanced lateral diffusion

Formation of ultra-shallow depth source/drain extensions for MOS transistors

Methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same

Method of forming miniaturized polycrystalline silicon gate electrodes using selective oxidation

Maintaining LDD series resistance of MOS transistors by retarding dopant segregation

Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion

Method for forming a semiconductor device with a tailored well profile

Distinguishing between dopant and line width variation components

Compensating for layout dimension effects in semiconductor device modeling

Bi-modal halo implantation

SOI MOSFET junction degradation using multiple buried amorphous layers

Method of forming transistor devices with different threshold voltages using halo implant shadowing

GLOBALFOUNDRIES INC

Transistor with asymmetric silicon germanium source region

Method for fabricating a semiconductor device having an extended stress liner

Self-aligned silicidation for replacement gate process

Semiconductor device and methods for fabricating same

Semiconductor devices having stressor regions and related fabrication methods

Transistor with asymmetric silicon germanium source region

Stress enhanced semiconductor device and methods for fabricating same

SULTAN AKIF

Semiconductor device and methods for fabricating same

Semiconductor devices having stressor regions and related fabrication methods

Method of fabricating multi-fingered semiconductor devices on a common substrate

SEN INDRADEEP

Self-aligned silicidation for replacement gate process

LI RUIGANG

Electronic device and method of biasing