Inventor

SINGHAL RONAK

US38 patents

⚠️ This page may combine multiple inventors who share the name “SINGHAL RONAK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SINGHAL RONAK

INTEL CORP

Breaking replay dependency loops in a processor using a rescheduled replay queue

Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter

Monitoring the operation of a processor

Multiple register memory access instructions, processors, methods, and systems

Prediction of load-store dependencies in a processing agent

Multiple register memory access instructions, processors, methods, and systems

Multiple register memory access instructions, processors, methods, and systems

Multiple register memory access instructions, processors, methods, and systems

Multiple register memory access instructions, processors, methods, and systems

Multiple register memory access instructions, processors, methods, and systems

Multiple register memory access instructions, processors, methods, and systems

Multiple register memory access instructions, processors, methods, and systems

Packed data element predication processors, methods, systems, and instructions

Packed data element predication processors, methods, systems, and instructions

Synchronizing recency information in an inclusive cache hierarchy

Method and apparatus for prefetching data to a lower level cache memory

Cache allocation with code and data prioritization

Cache allocation with code and data prioritization

Packed data element predication processors, methods, systems, and instructions

Apparatuses and methods for a processor architecture

Packed data element predication processors, methods, systems, and instructions

Misprediction-triggered local history-based branch prediction

Efficient hardware-based extraction of program instructions for critical paths

Apparatuses and methods for a processor architecture

Packed data element predication processors, methods, systems, and instructions

Monitoring the operation of a processor

Criticality based port scheduling

De-prioritizing speculative code lines in on-chip caches

Monitoring the operation of a processor

Load mechanism

Staggered execution stack for vector processing

Processors, methods, and systems to access a set of registers as either a plurality of smaller registers or a combined larger register

Systems, apparatuses, and methods for resource bandwidth enforcement

Instruction and logic for a cache prefetcher and dataless fill buffer

HINTON GLENN J

Controlling non-redundant execution in a redundant multithreading (RMT) processor

Obtaining data for redundant multithreading (RMT) execution

Redundant multithreading processor

KNAUTH LAURA A

SIMD processor with programmable counters externally configured to count executed instructions having operands of particular register size and element size combination