Inventor

MUKHERJEE SHUBHENDU S

US55 patents

⚠️ This page may combine multiple inventors who share the name “MUKHERJEE SHUBHENDU S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MUKHERJEE SHUBHENDU S

INTEL CORP

Incremental checkpointing in a multi-threaded architecture

Detecting errors in directory entries

Hardware recovery in a multi-threaded architecture

Periodic checkpointing in a redundantly multi-threaded architecture

Handling hot spots in interconnection networks

Fault free store data path for software implementation of redundant multithreading environments

Method and apparatus for reducing false error detection in a redundant multi-threaded system

Low power arbiters in interconnection routers

Vectoring process-kill errors to an application program

Implementing check instructions in each thread within a redundant multithreading environments

Reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system

Demand-based error correction

Converting merge buffer system-kill errors to process-kill errors

Generalized interlocked register cell (GICE)

Managing external memory updates for fault detection in redundant multithreading systems using speculative memory support

Fault detection using redundant virtual machines

Method and apparatus for lockstep processing on a fixed-latency interconnect

Method and apparatus for reducing false error detection in a microprocessor

Reducing false error detection in a microprocessor by tracking instructions neutral to errors

Method of handling errors

Fault detection

Method and apparatus for detecting transient faults via dynamic binary translation

Method and apparatus for protecting TLB&#39;s VPN from soft errors

MARVELL ASIA PTE LTD

Partitioning in a processor cache

System and method for implementing strong load ordering in a processor using a circular ordering ring

Shared mid-level data cache

Methods and systems for distributing memory requests

Methods and systems for distributing memory requests

Mid-level instruction cache

System and method for implementing strong load ordering in a processor using a circular ordering ring

System and method for implementing strong load ordering in a processor using a circular ordering ring

Processor data cache with shared mid-level cache and low-level cache

Methods and systems for distributing memory requests

HEWLETT PACKARD DEVELOPMENT CO

Simultaneous and redundantly threaded processor store instruction comparator

Input replicator for interrupts in a simultaneous and redundantly threaded processor

Cycle count replication in a simultaneous and redundantly threaded processor

Simultaneous and redundantly threaded processor uncached load address comparator and data value replication circuit

Slack fetch to improve performance in a simultaneous and redundantly threaded processor

Priority rules for reducing network message routing latency

Active load address buffer

CAVIUM INC

Merged TLB structure for multiple sequential address translations

Maintenance of cache and tags in a translation lookaside buffer

Collapsed address translation with multiple page sizes

Translation lookaside buffer management

Method and apparatus for conditional storing of data using a compare-and-swap based approach

CAVIUM LLC

Methods and systems for distributing memory requests

Prefetching data to reduce cache misses

WISCONSIN ALUMNI RES FOUND

Cacheable interface control registers for high speed data transfer

HINTON GLENN J

Obtaining data for redundant multithreading (RMT) execution

MUKHERJEE SHUBHENDU S

State history storage for synchronizing redundant processors

Method and apparatus for protecting TLB's VPN from soft errors