Inventor

KHOR CHOON WEI

MY2 patents

Patents

2 patents

US9348591B2May 24, 2016

Multi-level tracking of in-use state of cache lines

KIM ILHYUN2 citations54

US9158696B2Oct 13, 2015

Hiding instruction cache miss latency by running tag lookups ahead of the instruction accesses

KIM ILHYUN0 citations42