Inventor

BLASCO CONRADO

US30 patents

⚠️ This page may combine multiple inventors who share the name “BLASCO CONRADO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BLASCO CONRADO

APPLE INC

Systems and methods for optimizing authentication branch instructions

System and method for predicting memory dependence when a source register of a push instruction matches the destination register of a pop instruction

Branch prediction system

Methods for partially saving a branch predictor state

Split register file for operands of different sizes

Indirect branch predictor based on register operands

Storing taken branch information

Program counter capturing

Immediate branch recode that handles aliasing

Indirect branch predictor storing encrypted branch information fields and security tag for security protection

Fetch predition circuit for reducing power consumption in a processor

Reducing power consumption in a processor

History file for previous register mapping storage and last reference indication

Methods for partially preserving a branch predictor state

Systems and methods for optimizing authentication branch instructions

Indirect branch predictor storing encrypted branch information fields

Hierarchical reservation station

Zero cycle load bypass in a decode group

Marking valid return targets

Speculative writes to special-purpose register

Early loop buffer mode entry upon number of mispredictions of exit condition exceeding threshold

Program counter zero-cycle loads

Mechanism for allowing speculative execution of loads beyond a wait for event instruction

QUALCOMM INC

Compressing translation lookaside buffer (TLB) tags using a TLB metadata buffer in processor-based devices

Compressing translation lookaside buffer (TLB) tags using a TLB metadata buffer in processor-based devices

Mitigating pointer authentication code (PAC) attacks in processor-based devices

Performing fused shift and logical operations in processor-based devices

Technique for prefetching with a pointer prefetcher

Latency management in synchronization events

Using retired pages history for instruction translation lookaside buffer (TLB) prefetching in processor-based devices