Inventor

MUI MAN LUNG

US48 patents

⚠️ This page may combine multiple inventors who share the name “MUI MAN LUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MUI MAN LUNG

SANDISK CORP

Method for sensing negative threshold voltages in non-volatile storage using current sensing

Method of compensating variations along a word line in a non-volatile memory

Low noise sense amplifier array and method for nonvolatile memory

Nonvolatile memory with a current sense amplifier having a precharge circuit and a transfer gate coupled to a sense node

Sensing in non-volatile storage using pulldown to regulated source voltage to remove system noise

Low noise sense amplifier array and method for nonvolatile memory

Method for source bias all bit line sensing in non-volatile storage

Minimizing power noise during sensing in memory device

Memory device with power noise minimization during sensing

Complete word line look ahead with efficient data latch assignment in non-volatile memory read operations

Systems for complete word line look ahead with efficient data latch assignment in non-volatile memory read operations

Compensating source voltage drop in non-volatile storage

Non-volatile storage with source bias all bit line sensing

Non-volatile memory with compensation for variations along a word line

Non-volatile storage with current sensing of negative threshold voltages

Method for current sensing with biasing of source and P-well in non-volatile storage

Non-volatile storage with compensation for source voltage drop

Non-volatile storage using current sensing with biasing of source and P-Well

SANDISK TECHNOLOGIES INC

Compact high speed sense amplifier for non-volatile memory and hybrid lockout

Compensation for sub-block erase

Bit line resistance compensation

Optimized configurable NAND parameters

Temperature based compensation during verify operations for non-volatile storage

Bit line resistance compensation

Compact high speed sense amplifier for non-volatile memory

Fast-reading NAND flash memory

System for maintaining back gate threshold voltage in three dimensional NAND memory

Bit line resistance compensation

Select transistor tuning

Non-volatile memory and method with adjusted timing for individual programming pulses

Adaptive operation of three dimensional memory

Memory system with unverified program step

Compensation for sub-block erase

Systems and methods to avoid false verify and false read

Selection of data for redundancy calculation in three dimensional nonvolatile memory

NGUYEN HAO THAI

High speed sense amplifier array and method for non-volatile memory

Charge cycling by equalizing and regulating the source, well, and bit line levels during write operations for NAND flash memory: verify to program transition

Charge cycling by equalizing the source and bit line levels between pulses during no-verify write operations for NAND flash memory

Low noise sense amplifier array and method for nonvolatile memory

Charge cycling by equalizing and regulating the source, well, and bit line levels during write operations for NAND flash memory: program to verify transition

YANGTZE MEMORY TECH CO LTD

Method for programming a memory device to reduce retention error

Method for programming memory device to reduce retention error

Method for programming a memory system

Method for programming a memory system

WESTERN DIGITAL TECH INC

SSD operation in a nonoptimal memory environment

Linked XOR flash data protection scheme

OOWADA KEN

Temperature based compensation during verify operations for non-volatile storage

SANDISK TECHNOLOGIES LLC

Compact high speed sense amplifier for non-volatile memory with reduced layout area and power consumption