Inventor

MIYAZOE HIROYUKI

US91 patents

⚠️ This page may combine multiple inventors who share the name “MIYAZOE HIROYUKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MIYAZOE HIROYUKI

IBM

Multivalent oxide cap for analog switching resistive memory

Scaled cross bar array with undercut electrode

Electrode pair fabrication using directed self assembly of diblock copolymers

Sputter and surface modification etch processing for metal patterning in integrated circuits

Crossbar resistive memory array with highly conductive copper/copper alloy electrodes and silver/silver alloys electrodes

Crossbar resistive memory array with highly conductive copper/copper alloy electrodes and silver/silver alloys electrodes

Scaled cross bar array with undercut electrode

Selective sputtering with light mass ions to sharpen sidewall of subtractively patterned conductive metal layer

Self-aligned pitch split for unidirectional metal wiring

Stacked graphene field-effect transistor

Dielectric tone inversion materials

Dielectric tone inversion materials

Subtractive plasma etching of a blanket layer of metal or metal alloy

Optimal device structures for back-end-of-line compatible mixed ionic electronic conductors materials

Gate-all-around field effect transistor using template-assisted-slective-epitaxy

Resistive switching memory with replacement metal electrode

Directed self-assembly for copper patterning

Crossbar resistive memory array with highly conductive copper/copper alloy electrodes and silver/silver alloys electrodes

Thin film interconnects with large grains

Hybrid subtractive etch/metal fill process for fabricating interconnects

High aspect ratio patterning of hard mask materials by organic soft masks

Stacked graphene field-effect transistor

Hybrid subtractive etch/metal fill process for fabricating interconnects

Resistive memory crossbar array with top electrode inner spacers

Resistive memory crossbar array with top electrode inner spacers

Selective dry etch for directed self assembly of block copolymers

Magnetic tunnel junction patterning using low atomic weight ion sputtering

Interconnects based on subtractive etching of silver

Sputter etch processing for heavy metal patterning in integrated circuits

Sidewall image transfer for heavy metal patterning in integrated circuits

Interconnects based on subtractive etching of silver

Localized anneal of ferroelectric dielectric

Redundant bottom pad and sacrificial via contact for process induced RRAM forming

Process-induced forming of oxide RRAM

Conductive bridging random access memory formed using selective barrier metal removal

Non-volatile memory structure and method for low programming voltage for cross bar array

Semiconductor memory devices formed using selective barrier metal removal

Resistive switching memory with replacement metal electrode

High-resistance memory devices

Oxygen vacancy and filament-loss protection for resistive switching devices

Multivalent oxide cap for analog switching resistive memory

APPLIED MATERIALS INC

Copper residue chamber clean

Selective sputtering for pattern transfer

GLOBALFOUNDRIES INC

Low-temperature sidewall image transfer process using ALD metals, metal oxides and metal nitrides

Low energy etch process for nitrogen-containing dielectric layer

GUILLORN MICHAEL A

Tone inversion of self-assembled self-aligned structures

Tone inversion of self-assembled self-aligned structures

BRINK MARKUS

Low energy etch process for nitrogen-containing dielectric layer

High fidelity patterning employing a fluorohydrocarbon-containing polymer

TOKYO ELECTRON LTD

Oxygen-free plasma etching for contact etching of resistive random access memory