Inventor

BIRAN GIORA

IL87 patents

⚠️ This page may combine multiple inventors who share the name “BIRAN GIORA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BIRAN GIORA

IBM

Interrupt mechanism on an IO adapter that supports virtualization

Method and apparatus for address translation on PCI bus over infiniband network

Address protection using a hardware-defined application key

Method for dynamic management of TCP reassembly buffers

Network adapter with embedded deep packet processing

System and method for virtual adapter resource allocation matrix that defines the amount of resources of a physical I/O adapter

System and method for modification of virtual adapter resources in a logically partitioned data processing system

Method for virtual resource initialization on a physical adapter that supports virtual resources

Method, system and program product for differentiating between virtual hosts on bus transactions and associating allowable memory access for an input/output adapter that supports virtualization

System and method for host initialization for an adapter that supports virtualization

Reducing number of write operations relative to delivery of out-of-order RDMA send messages by managing reference counter

Data transfer error checking

System and method for virtual adapter resource allocation matrix that defines the amount of resources of a physical I/O adapter

Increasing TCP re-transmission process speed

Descriptor prefetch mechanism for high latency and out of order DMA device

System and method for efficient implementation of a shared receive queue

Controlling flow of data between data processing systems via a memory

Methods for the submission of accelerator commands and corresponding command structures to remote hardware accelerator engines over an interconnect link

Asynchronous dual-queue interface for use in network acceleration architecture

Association of memory access through protection attributes that are associated to an access control level on a PCI adapter that supports virtualization

Method of constructing an approximated dynamic Huffman table for use in data compression

Network acceleration architecture

Method and apparatus for data decompression in the presence of memory hierarchies

Method, system, and computer program product for virtual adapter destruction on a physical adapter that supports virtual adapters

Asynchronous completion notification for an RDMA system

Method for virtual adapter destruction on a physical adapter that supports virtual adapters

Method and system for fully trusted adapter validation of addresses referenced in a virtual host transfer request

System, method, and computer program product for a fully trusted adapter validation of incoming memory mapped I/O operations on a physical adapter that supports virtual adapters or virtual resources

Application and verb resource management

Proactive voltage droop reduction and/or mitigation in a processor core

Barrier and interrupt mechanism for high latency and out of order DMA device

Method for performing a direct memory access block move in a direct memory access device

Controlling flow of data between data processing systems via a memory

Wire speed reassembly of data frames

Computer system architecture for a processor connected to a high speed bus transceiver

Method of optimizing buffer usage of virtual channels of a physical communication link and apparatuses for performing the same

Native virtualization on a partially trusted adapter using PCI host bus, device, and function number for identification

Native virtualization on a partially trusted adapter using PCI host bus, device, and function number for identification

Completion coalescing by TCP receiver

Proactive voltage droop reduction and/or mitigation in a processor core

Instructions controlling access to shared registers of a multi-threaded processor

BIRAN GIORA

Device, system and method of modification of PCI express packet digest

Methods for the transmission of accelerator commands and corresponding command structure to remote hardware accelerator engines over an interconnect link

Algorithm engine for use in a pattern matching accelerator

Performance monitoring mechanism for use in a pattern matching accelerator

Method of accelerating dynamic Huffman decompaction within the inflate algorithm

Method of hybrid compression acceleration utilizing special and general purpose processors

ACHILLES HEATHER D

Utilization of special purpose accelerators using general purpose processors

BASS BRIAN MITCHELL

Method and apparatus for concurrent and stateful decompression of multiple compressed data streams

GLASS LIOR

Compression algorithm incorporating a feedback loop for dynamic selection of a predefined Huffman dictionary