Inventor

CHUN DEXTER TAMIO

US61 patents

⚠️ This page may combine multiple inventors who share the name “CHUN DEXTER TAMIO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHUN DEXTER TAMIO

QUALCOMM INC

Systems and methods to refresh DRAM based on temperature and based on calibration data

System and method for temperature compensated refresh of dynamic random access memory

Robust and high-speed memory access with adaptive interface timing

System and memory with configurable metadata portion

Partial refresh technique to save memory refresh power

Power saving techniques for memory systems by consolidating data in data lanes of a memory bus

Systems and methods for providing non-power-of-two flash cell mapping

Systems and methods for recovering from uncorrected DRAM bit errors

System-in-package with interposer pitch adapter

Dynamic random access memory (DRAM) backchannel communication systems and methods

Protected data streaming between memories

Partial refresh technique to save memory refresh power

Power saving techniques for memory systems by consolidating data in data lanes of a memory bus

Partial refresh technique to save memory refresh power

Memory access management for low-power use cases of a system on chip via secure non-volatile random access memory

Unified memory controller for heterogeneous memory on a multi-chip package

Systems and methods for optimizing memory power consumption in a heterogeneous system memory

System and method for odd modulus memory channel interleaving

Non-volatile random access system memory with DRAM program caching

Systems, methods, and computer programs for resolving dram defects

Power-reducing memory subsystem having a system cache and local resource management

System and method for thermoelectric memory temperature control

Method and apparatus for in-system repair of memory in burst refresh

Method and apparatus for non-volatile RAM error re-mapping

Enhanced data clock operations in memory

Method and apparatus for in-system management and repair of semi-conductor memory failure

Dynamic control of signaling power based on an error rate

Methods and apparatuses for memory power reduction

Systems and methods for providing improved latency in a non-uniform memory architecture

System and memory with configurable error-correction code (ECC) data protection and related methods

Enhanced data clock operations in memory

Partial refresh technique to save memory refresh power

Optimized error-correcting code (ECC) for data protection

Dynamic link error protection in memory systems

Dynamic link error protection in memory systems

Dynamic mapping of applications on NVRAM/DRAM hybrid memory

Memory with system ECC

Memory with dynamic voltage scaling

System and method for modem-directed application processor boot flow

Multi-layer heat dissipating apparatus for an electronic device

Methods and apparatus for in-memory device access control

Adaptive power management of dynamic random access memory

Optimized error-correcting code (ECC) for data protection

Power-reducing memory subsystem having a system cache and local resource management

System and method for flash read cache with adaptive pre-fetch

Dynamic voltage adjustment of an I/O interface signal

Method and apparatus for multiple-bit DRAM error recovery

Dynamic random access memory (DRAM) backchannel communication systems and methods

Systems and methods for providing error code detection using non-power-of-two flash cell mapping

CHUN DEXTER TAMIO

Method and apparatus for securely booting from an external storage device