Inventor

MANNAVA PHANINDRA KUMAR

US33 patents

⚠️ This page may combine multiple inventors who share the name “MANNAVA PHANINDRA KUMAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MANNAVA PHANINDRA KUMAR

ADVANCED RISC MACH LTD

Interface circuitry for exchanging information with master, home, and slave nodes using different data transfer protocols

Apparatus and method for handling cache maintenance operations

Access control

Read-with overridable-invalidate transaction

Memory interface having data signal path and tag signal path

Memory controller having data access hint message for specifying the given range of one or more memory addresses

Data processing apparatus with snoop request address alignment and snoop response time alignment

Efficient support for variable width data channels in an interconnect network

Cache content management

Read transaction tracker lifetimes in a coherent interconnect system

Separating completion and data responses for higher read throughput and lower link utilization in a data processing network

Data processing network with flow compaction for streaming data transfer

Data processing system for a home node to authorize a master to bypass the home node to directly send data to a slave

Writing zero data

Forwarding responses to snoop requests

Transfer protocol in a data processing network

Responding to snoop requests

Cache bypass

Data elision

Exclusivity in circuitry having a home node providing coherency control

Interconnect circuitry and a method of operating such interconnect circuitry

Memory controller having data access hint message for specifying the given range of one or more memory addresses

Non-forwardable transfers

Runtime configuration of a data processing system

Data processing

Cache maintenance operations in a data processing system

Dynamic adaptation of direct memory transfer in a data processing system with mismatched data-bus widths

Compare-and-swap transaction

MANNAVA PHANINDRA KUMAR

Coherency controller and method for data hazard handling for copending data access requests

Dynamic resource allocation for transaction requests issued by initiator devices to recipient devices

Synchronisation of data processing systems

JALAL JAMSHED

Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels

FLANDERS WILLIAM HENRY

Data processing apparatus having first and second protocol domains, and method for the data processing apparatus