Inventor

RISSO ALESSANDRO

US18 patents

⚠️ This page may combine multiple inventors who share the name “RISSO ALESSANDRO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RISSO ALESSANDRO

QUALCOMM INC

On the fly interleaving/rate matching and deinterleaving/de-rate matching for 5G NR

Techniques for decoding downlink control information with different sizes in wireless communications

Combining decision metrics of a scrambled payload

Parity check for list-based decoding

Techniques for masking and unmasking cyclic redundancy check bits for early termination of decoding

Control of error correction decoder operation and usage in a receiver device

Non-binary polar codes for probabilistic amplitude shaping

Single step in-place operation method for 5G NR de-interleaving, de-rate matching, and HARQ combination

Tone classification for physical channels with multiplexed data

Polar coding Reed-Muller node optimization using Fast Hadamard Transform

Error detection for a wireless channel

ST MICROELECTRONICS INC

Apparatus and method for implementing a ROM patch using a lockable cache

Closely coupled vector sequencers for a read channel pipeline

Max-Log-MAP equivalence log likelihood ratio generation soft Viterbi architecture system and method

KAYNAK MUSTAFA N

Rendering data write errors detectable

Detecting data-write errors

RISSO ALESSANDRO

System and method for map detector for symbol based error correction codes

PARTHASARATHY SIVAGNANAM

Max-log-map equivalence log likelihood ratio generation soft viterbi architecture system and method