Inventor
FEDERICI JAMES L
US5 patents
Patents
5 patentsUS5875201AFeb 23, 1999
Second level cache having instruction cache parity error control
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US5617375AApr 1, 1997
Dayclock carry and compare tree
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US6697925B1Feb 24, 2004
Use of a cache ownership mechanism to synchronize multiple dayclocks
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US6055607AApr 25, 2000
Interface queue with bypassing capability for main storage unit
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US6857049B1Feb 15, 2005
Method for managing flushes with the cache
UNISYS CORP1 citations51