Inventor

HUANG CHENG-YING

US92 patents

⚠️ This page may combine multiple inventors who share the name “HUANG CHENG-YING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUANG CHENG-YING

INTEL CORP

Gate-all-around integrated circuit structures having depopulated channel structures using selective bottom-up approach

Transistor with isolation below source and drain

Forksheet transistors with dielectric or conductive spine

Stacked forksheet transistors

Stacked nanowire transistor structure with different channel geometries for stress

Interconnect techniques for electrically connecting source/drain regions of stacked transistors

Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches

Interconnect techniques for electrically connecting source/drain regions of stacked transistors

Stacked transistors having device strata with different channel widths

III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts

Stacked transistors with different gate lengths in different device strata

Ferroelectric gate stack for band-to-band tunneling reduction

Stacked transistors with Si PMOS and high mobility thin film transistor NMOS

Non-silicon N-Type and P-Type stacked transistors for integrated circuit devices

Vertical tunneling field-effect transistors

Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication

Transistor structure with indium phosphide channel

Source-channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)

Transistor with isolation below source and drain

Three-dimensional integrated circuits (3DICs) including upper-level transistors with epitaxial source and drain material

Stacked transistor architecture having diverse fin geometry

Device isolation by fixed charge

High mobility asymmetric field effect transistors with a band-offset semiconductor drain spacer

Forksheet transistors with dielectric or conductive spine

Gate-all-around integrated circuit structures having depopulated channel structures using selective bottom-up approach

Leave-behind protective layer having secondary purpose

Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material

Channel layer formed in an art trench

Non-silicon N-type and P-type stacked transistors for integrated circuit devices

Ferroelectric gate stack for band-to-band tunneling reduction

Thin film transistor structures with regrown source and drain

Vertical tunneling field-effect transistors

Vertical diode in stacked transistor architecture

Field effect transistors with wide bandgap materials

Transistors stacked on front-end p-type transistors

Tunneling field effect transistors

Source to channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)

Reduced transistor resistance using doped layer

Top gate recessed channel CMOS thin film transistor and methods of fabrication

Transistor with isolation below source and drain

Sideways vias in isolation areas to contact interior layers in stacked devices

Gate-all-around integrated circuit structures having depopulated channel structures using selective bottom-up approach

Forming an oxide volume within a fin

Stacked source-drain-gate connection and process for forming such

Leave-behind protective layer having secondary purpose

Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material

Sideways vias in isolation areas to contact interior layers in stacked devices

Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication

Stacked source-drain-gate connection and process for forming such

WANN CLEMENT HSINGJEN

Re-growing source/drain regions from un-relaxed silicon layer