Inventor

MA SEAN T

US63 patents

⚠️ This page may combine multiple inventors who share the name “MA SEAN T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MA SEAN T

INTEL CORP

Top-gate doped thin film transistor

Transistor with isolation below source and drain

Top-gate doped thin film transistor

Structures and methods for memory cells

Gate spacing in integrated circuit structures

Ferroelectric gate stack for band-to-band tunneling reduction

Source/drain regions in integrated circuit structures

Transistor with isolation below source and drain

Device isolation by fixed charge

High mobility field effect transistors with a band-offset semiconductor source/drain spacer

High mobility field effect transistors with a retrograded semiconductor source/drain

Structures and methods for memory cells

Top-gate doped thin film transistor

Field effect transistors with gate electrode self-aligned to semiconductor fin

Non-planar transistor arrangements with asymmetric gate enclosures

Ferroelectric gate stack for band-to-band tunneling reduction

Thin film transistor with charge trap layer

Field effect transistors with wide bandgap materials

Source to channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)

Field effect transistors with gate electrode self-aligned to semiconductor fin

FINFET transistor having a doped subfin structure to reduce channel to substrate leakage

High-mobility field effect transistors with wide bandgap fin cladding

Semiconductor device with released source and drain

Reduced transistor resistance using doped layer

Source/drain regions in integrated circuit structures

Gate spacing in integrated circuit structures

3D 1T1C stacked dram structure and method to fabricate

Transistor with isolation below source and drain

Device contact sizing in integrated circuit structures

Source/drain regions in integrated circuit structures

3D 1T1C stacked DRAM structure and method to fabricate

Subfin leakage suppression using fixed charge

Isolation regions in integrated circuit structures

Vertically stacked memory elements with air gap

Vertically stacked transistors in a fin

Source/drain regions in integrated circuit structures

Device contact sizing in integrated circuit structures

Source/drain recess etch stop layers and bottom wide-gap cap for III-V MOSFETs

Field effect transistors with reduced electric field by thickening dielectric on the drain side

Isolation regions in integrated circuit structures

Group III-V semiconductor devices having asymmetric source and drain structures

Vertically stacked transistors in a pin

Art trench spacers to enable fin release for non-lattice matched channels

Dopant diffusion barrier for source/drain to curb dopant atom diffusion

Device contacts in integrated circuit structures

Source/drain regions in integrated circuit structures

High performance semiconductor oxide material channel regions for NMOS

Indium-containing fin of a transistor device with an indium-rich core

Transistors with high density channel semiconductor over dielectric material

TAHOE RES LTD

FINFET transistor having a doped sub fin structure to reduce channel to substrate leakage