Inventor

CHOI JUNGHWAN

KR91 patents

⚠️ This page may combine multiple inventors who share the name “CHOI JUNGHWAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHOI JUNGHWAN

SAMSUNG ELECTRONICS CO LTD

Multi channel semiconductor device having multi dies and operation method thereof

Memory device and memory system including the same

Quadrature error correction circuit and semiconductor memory device including the same

Multi channel semiconductor device having multi dies and operation method thereof

Multi channel semiconductor device having multi dies and operation method thereof

Memory device for receiving one clock signal as a multi-level signal and restoring original data encoded into the clock signal and method of operating the same

Semiconductor memory device and memory system including the same

Data processing device and memory system including the same

Memory device for generating pulse amplitude modulation-based DQ signal and memory system including the same

Quadrature error correction circuit and semiconductor memory device including the same

Offset detector circuit for differential signal generator, receiver, and method of compensating for offset of differential signal generator

Memory device supporting a high-efficient input/output interface and a memory system including the memory device

Memory device, method of calibrating signal level thereof, and memory system having the same

Probe device, test device, and test method for semiconductor device

Transmitters for generating multi-level signals and memory system including the same

Memory package and storage device including the same

Method and apparatus for analyzing communication environments and designing networks in consideration of trees

Memory device supporting a high-efficient input/output interface and a memory system including the memory device

Memory device, controller controlling the same, memory system including the same, and operating method thereof

Analysis method and apparatus for distributed-processing-based network design in wireless communication system

Delay circuit and clock error correction device including the same

Multi-level signal receivers and memory systems including the same

Digital phase locked loop and methods of operating same

Low dropout regulator and memory device including the same

Receiver for receiving multi-level signal and memory device including the same

Semiconductor memory module including nonvolatile memory devices

Method of generating a multi-level signal using a selective level change, a method of transmitting data using the same, and a transmitter and memory system performing the same

Memory device and operating method of a memory device

Memory device supporting a high-efficient input/output interface and a memory system including the memory device

Memory interface and semiconductor memory device and semiconductor device including the same

Memory device supporting a high-efficient input/output interface and a memory system including the memory device

Translation device, test system including the same, and memory system including the translation device

Transmitter circuit including selection circuit, and method of operating the selection circuit

Clock signal delay path unit and semiconductor memory device including the same

Clock converting circuit with symmetric structure

Memory device, controller controlling the same, memory system including the same, and operating method thereof

Method of generating a multi-level signal using a selective level change, a method of transmitting data using the same, and a transmitter and memory system performing the same

Translation device, test system including the same, and memory system including the translation device

Memory devices configured to generate pulse amplitude modulation-based DQ signals, memory controllers, and memory systems including the memory devices and the memory controllers

Memory device for generating data strobe signal based on pulse amplitude modulation, memory controller, and memory system including the same

Data converter for cancelling offset voltage

Nonvolatile memory device including power gating circuit and input/output circuit of a nonvolatile memory device

Encoding and decoding apparatuses and methods for implementing multi-mode coding

Semiconductor memory device and memory system including the same

Transmitter and receiver for 3-level pulse amplitude modulation signaling and system including the same

Encoding and decoding apparatuses and methods for implementing multi-mode coding

Multi channel semiconductor device having multi dies and operation method thereof

Multi channel semiconductor device having multi dies and operation method thereof

HYUN SEOKHUN

Delay locked loop circuit and operation method thereof

KIM JEONG-KYOUM

Memory chip package having optically and electrically connected chips, memory system having the same and driving method thereof