Inventor
YOON SEUNG WOOK
SG24 patents
⚠️ This page may combine multiple inventors who share the name “YOON SEUNG WOOK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
STATS CHIPPAC PTE LTD
9 patentsUS10475779B2Nov 12, 2019
Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
STATS CHIPPAC PTE LTD7 citations84
US12094729B2Sep 17, 2024
Semiconductor device with encapsulant deposited along sides and surface edge of semiconductor die in embedded WLCSP
STATS CHIPPAC PTE LTD2 citations72
US10515828B2Dec 24, 2019
Method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP
STATS CHIPPAC PTE LTD1 citations72
US10446459B2Oct 15, 2019
Semiconductor device and method of forming encapsulated wafer level chip scale package (EWLCSP)
STATS CHIPPAC PTE LTD2 citations72
US11222793B2Jan 11, 2022
Semiconductor device with encapsulant deposited along sides and surface edge of semiconductor die in embedded WLCSP
STATS CHIPPAC PTE LTD0 citations62
US11961764B2Apr 16, 2024
Semiconductor device and method of making a wafer-level chip-scale package
STATS CHIPPAC PTE LTD0 citations61
US11011423B2May 18, 2021
Semiconductor device and method of using a standardized carrier in semiconductor packaging
STATS CHIPPAC PTE LTD0 citations61
US10903304B2Jan 26, 2021
Semiconductor device and method of forming inductor over insulating material filled trench in substrate
STATS CHIPPAC PTE LTD0 citations57
US10181423B2Jan 15, 2019
Semiconductor device and method of using a standardized carrier in semiconductor packaging
STATS CHIPPAC PTE LTD0 citations50
STATS CHIPPAC LTD
8 patentsUS9064936B2Jun 23, 2015
Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
STATS CHIPPAC LTD58 citations98
US9768155B2Sep 19, 2017
Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
STATS CHIPPAC LTD14 citations92
US9293401B2Mar 22, 2016
Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP)
STATS CHIPPAC LTD11 citations84
US9496195B2Nov 15, 2016
Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP
STATS CHIPPAC LTD4 citations83
US9620413B2Apr 11, 2017
Semiconductor device and method of using a standardized carrier in semiconductor packaging
STATS CHIPPAC LTD4 citations82
US9704769B2Jul 11, 2017
Semiconductor device and method of forming encapsulated wafer level chip scale package (EWLCSP)
STATS CHIPPAC LTD3 citations72
US9224693B2Dec 29, 2015
Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier
STATS CHIPPAC LTD3 citations63
US9640603B2May 2, 2017
Semiconductor device and method of forming inductor over insulating material filled trench in substrate
STATS CHIPPAC LTD1 citations47
KOO JUN MO
2 patentsUS9224647B2Dec 29, 2015
Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
KOO JUN MO109 citations97
US8993377B2Mar 31, 2015
Semiconductor device and method of bonding different size semiconductor die at the wafer level
KOO JUN MO70 citations97
JCET SEMICONDUCTOR SHAOXING CO LTD
2 patentsUS11257729B2Feb 22, 2022
Semiconductor device and method of forming encapsulated wafer level chip scale package (eWLCSP)
JCET SEMICONDUCTOR SHAOXING CO LTD0 citations61
US10622293B2Apr 14, 2020
Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLB-MLP)
JCET SEMICONDUCTOR SHAOXING CO LTD0 citations51