Inventor

MAJUMDAR AMITAVA

US65 patents

⚠️ This page may combine multiple inventors who share the name “MAJUMDAR AMITAVA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MAJUMDAR AMITAVA

MICRON TECHNOLOGY INC

Socket design for a memory device

Non-contact measurement of memory cell threshold voltage

Non-contact electron beam probing techniques and related structures

Non-contact electron beam probing techniques and related structures

Electron beam probing techniques and related structures

Socket design for a memory device

Memory device security and row hammer mitigation

Socket design for a memory device

Adjustable programming pulses for a multi-level cell

Instant write scheme with delayed parity/raid

Method and memory system for writing data to dram submodules based on the data traffic demand

Cache memory with randomized eviction

Cache memory with randomized eviction

Self-selecting memory cells configured to store more than one bit per memory cell

Row hammer telemetry

Memory failure prediction and mitigation

Leakage source detection for memory with varying conductive path lengths

Leakage source detection by scanning access lines

System for predicting properties of structures, imager system, and related methods

Error detection, correction, and media management on a dram device

Error detection, correction, and media management on a memory device

Selective per die DRAM PPR for memory device

Electron beam probing techniques and related structures

XILINX INC

Heterogeneous integration of integrated circuit device and companion device

Circuits for and methods of implementing a design for testing and debugging with dual-edge clocking

Test circuits for testing a die stack

Clock stoppage in integrated circuits with multiple asynchronous clock domains

Circuits for and methods of testing the operation of an input/output port

Time-to-digital conversion

Efficient system debug infrastructure for tiled architecture

Restoring memory data integrity

Integrated circuit skew determination

Interposer-less stack die interconnect

Testing memory elements using an internal testing interface

Method and apparatus for testing interposer dies prior to assembly

Runtime measurement of process variations and supply voltage characteristics

Programmable dynamic clock stretch for at-speed debugging of integrated circuits

Scalable scan architecture for multi-circuit block arrays

Circuit architecture for expanded design for testability functionality

Testing for shorts between internal nodes of a power distribution grid

Hybrid synchronous and asynchronous control for scan-based testing

Intra-chip and inter-chip data protection

SUN MICROSYSTEMS INC

Automatic generation and validation of memory test models

Built-in self-test (BIST) of memory interconnect

Method and apparatus for generating and verifying libraries for ATPG tool

Instruction-based built-in self-test (BIST) of external memory

SYNOPSYS INC

Circuit for efficiently testing memory and shadow logic of a semiconductor integrated circuit

Circuit for efficiently testing memory and shadow logic of a semiconductor integrated circuit

Method for minimizing ground bounce during DC parametric tests using boundary scan register

MAJUMDAR AMITAVA

Method and apparatus for AC scan testing with distributed capture and shift logic