Inventor
YU CHUN-CHI
TW46 patents
⚠️ This page may combine multiple inventors who share the name “YU CHUN-CHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
REALTEK SEMICONDUCTOR CORP
26 patentsUS10998061B1May 4, 2021
Memory system and memory access interface device thereof
REALTEK SEMICONDUCTOR CORP9 citations85
US10978118B1Apr 13, 2021
DDR SDRAM signal calibration device and method
REALTEK SEMICONDUCTOR CORP7 citations84
US10522204B1Dec 31, 2019
Memory signal phase difference calibration circuit and method
REALTEK SEMICONDUCTOR CORP14 citations84
US10741231B1Aug 11, 2020
Memory access interface device including phase and duty cycle adjusting circuits for memory access signals
REALTEK SEMICONDUCTOR CORP4 citations73
US9570130B2Feb 14, 2017
Memory system and memory physical layer interface circuit
REALTEK SEMICONDUCTOR CORP6 citations73
US10698846B2Jun 30, 2020
DDR SDRAM physical layer interface circuit and DDR SDRAM control device
REALTEK SEMICONDUCTOR CORP4 citations72
US10643685B1May 5, 2020
Control circuit, sampling circuit for synchronous dynamic random-access memory, method of reading procedure and calibration thereof
REALTEK SEMICONDUCTOR CORP2 citations72
US10630289B1Apr 21, 2020
On-die-termination circuit and control method for of the same
REALTEK SEMICONDUCTOR CORP3 citations72
US10269443B2Apr 23, 2019
Memory device and test method of the same
REALTEK SEMICONDUCTOR CORP6 citations72
US9355708B2May 31, 2016
Memory control circuit for adjusting reference voltage and associated memory control method
REALTEK SEMICONDUCTOR CORP5 citations72
US10916278B1Feb 9, 2021
Memory controller and memory data receiving method for generate better sampling clock signal
REALTEK SEMICONDUCTOR CORP4 citations71
US11315656B1Apr 26, 2022
Detection circuit and detection method
REALTEK SEMICONDUCTOR CORP0 citations61
US11270745B2Mar 8, 2022
Method of foreground auto-calibrating data reception window and related device
REALTEK SEMICONDUCTOR CORP1 citations61
US10998020B1May 4, 2021
Memory system and memory access interface device thereof
REALTEK SEMICONDUCTOR CORP1 citations61
US9135980B2Sep 15, 2015
Memory control circuit and method of controlling data reading process of memory module
REALTEK SEMICONDUCTOR CORP2 citations61
US12417795B2Sep 16, 2025
Physical layer circuit, write leveling training circuit and method for calibrating access control signal transmitted to memory device
REALTEK SEMICONDUCTOR CORP0 citations52
US12288583B2Apr 29, 2025
Memory controller and method for calibrating data reception window
REALTEK SEMICONDUCTOR CORP0 citations52
US12088359B2Sep 10, 2024
Receiver of communication system and eye diagram measuring method
REALTEK SEMICONDUCTOR CORP0 citations52
US11816352B2Nov 14, 2023
Electronic device, data strobe gate signal generator circuit and data strobe gate signal generating method
REALTEK SEMICONDUCTOR CORP0 citations52
US12300330B2May 13, 2025
Memory system and memory access interface device thereof for supporting different speed modes
REALTEK SEMICONDUCTOR CORP0 citations51
US12188982B2Jan 7, 2025
Test method for delay circuit and test circuitry
REALTEK SEMICONDUCTOR CORP0 citations51
US11823770B1Nov 21, 2023
Memory system and memory access interface device thereof
REALTEK SEMICONDUCTOR CORP0 citations51
US10056124B2Aug 21, 2018
Memory control device for repeating data during a preamble signal or a postamble signal and memory control method
REALTEK SEMICONDUCTOR CORP0 citations51
US12429902B2Sep 30, 2025
Memory system, memory access interface device and operation method thereof
REALTEK SEMICONDUCTOR CORP0 citations50
US12009056B2Jun 11, 2024
Data transmission apparatus and method having clock gating mechanism
REALTEK SEMICONDUCTOR CORP0 citations50
US11978497B2May 7, 2024
DDR SDRAM signal calibration device and method
REALTEK SEMICONDUCTOR CORP0 citations50
UNITED MICROELECTRONICS CORP
16 patentsUS9653404B1May 16, 2017
Overlay target for optically measuring overlay alignment of layers formed on semiconductor wafer
UNITED MICROELECTRONICS CORP10 citations80
US9482964B2Nov 1, 2016
Overlap mark set and method for selecting recipe of measuring overlap error
UNITED MICROELECTRONICS CORP4 citations72
US9007571B2Apr 14, 2015
Measurement method of overlay mark
UNITED MICROELECTRONICS CORP5 citations69
US12106962B2Oct 1, 2024
Patterning method and overlay measurement method
UNITED MICROELECTRONICS CORP0 citations61
US12147163B2Nov 19, 2024
Method for correcting critical dimension measurements of lithographic tool
UNITED MICROELECTRONICS CORP0 citations60
US9400435B2Jul 26, 2016
Method of correcting overlay error
UNITED MICROELECTRONICS CORP2 citations60
US11043460B2Jun 22, 2021
Measurement method of overlay mark structure
UNITED MICROELECTRONICS CORP0 citations58
US10811362B2Oct 20, 2020
Overlay mark structure and measurement method thereof
UNITED MICROELECTRONICS CORP1 citations58
US12211699B2Jan 28, 2025
Method of removing step height on gate structure
UNITED MICROELECTRONICS CORP0 citations56
US9147601B2Sep 29, 2015
Method of forming via hole
UNITED MICROELECTRONICS CORP0 citations52
US9136140B2Sep 15, 2015
Patterning method
UNITED MICROELECTRONICS CORP0 citations52
US10916636B2Feb 9, 2021
Method of forming gate
UNITED MICROELECTRONICS CORP0 citations51
US9448471B2Sep 20, 2016
Photo-mask and method of manufacturing semiconductor structures by using the same
UNITED MICROELECTRONICS CORP0 citations51
US9494873B2Nov 15, 2016
Asymmetry compensation method used in lithography overlay process
UNITED MICROELECTRONICS CORP0 citations50
US7476472B2Jan 13, 2009
Method for designing photomask
UNITED MICROELECTRONICS CORP0 citations47
US7633601B2Dec 15, 2009
Method and related operation system for immersion lithography
UNITED MICROELECTRONICS CORP0 citations34