P

Inventor

JOURDAN STEPHAN

US39 patents
⚠️ This page may combine multiple inventors who share the name “JOURDAN STEPHAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

24 patents
US6912648B2Jun 28, 2005

Stick and spoke replay with selectable delays

INTEL CORP78 citations98
US7949887B2May 24, 2011

Independent power control of processing cores

INTEL CORP43 citations97
US6950924B2Sep 27, 2005

Passing decoded instructions to both trace cache building engine and allocation module operating in trace cache or decoder reading state

INTEL CORP43 citations95
US7136992B2Nov 14, 2006

Method and apparatus for a stew-based loop predictor

INTEL CORP38 citations93
US6952764B2Oct 4, 2005

Stopping replay tornadoes

INTEL CORP29 citations93
US7533252B2May 12, 2009

Overriding a static prediction with a level-two predictor

INTEL CORP17 citations81
US6848031B2Jan 25, 2005

Parallel searching for an instruction at multiple cache levels

INTEL CORP9 citations74
US7404065B2Jul 22, 2008

Flow optimization and prediction for VSSE memory operations

INTEL CORP7 citations73
US11526205B2Dec 13, 2022

Methods and apparatus to implement always-on context sensor hubs for processing multiple different types of data inputs

INTEL CORP2 citations72
US7913064B2Mar 22, 2011

Operation frame filtering, building, and execution

INTEL CORP2 citations62
US7533247B2May 12, 2009

Operation frame filtering, building, and execution

INTEL CORP2 citations62
US7181597B2Feb 20, 2007

Decoding instructions for trace cache resume state in system passing decoded operations to both trace cache and execution allocation module

INTEL CORP4 citations62
US12360585B2Jul 15, 2025

Methods and apparatus to implement always-on context sensor hubs for processing multiple different types of data inputs

INTEL CORP0 citations61
US7130965B2Oct 31, 2006

Apparatus and method for store address for store address prefetch and line locking

INTEL CORP3 citations61
US7454596B2Nov 18, 2008

Method and apparatus for partitioned pipelined fetching of multiple execution threads

INTEL CORP2 citations56
US10635155B2Apr 28, 2020

Independent power control of processing cores

INTEL CORP0 citations52
US10613610B2Apr 7, 2020

Independent power control of processing cores

INTEL CORP0 citations52
US10534419B2Jan 14, 2020

Independent power control of processing cores

INTEL CORP0 citations52
US10095300B2Oct 9, 2018

Independent power control of processing cores

INTEL CORP0 citations52
US9841803B2Dec 12, 2017

Independent power control of processing cores

INTEL CORP0 citations52
US8825989B2Sep 2, 2014

Technique to perform three-source operations

INTEL CORP0 citations52
US7457938B2Nov 25, 2008

Staggered execution stack for vector processing

INTEL CORP1 citations52
US7457932B2Nov 25, 2008

Load mechanism

INTEL CORP0 citations52
US12026304B2Jul 2, 2024

Smart display panel apparatus and related methods

INTEL CORP0 citations48

GUNTHER STEPHEN H

7 patents

JOURDAN STEPHAN

3 patents

RAPPOPORT LIHU

1 patent

RONEN RONNY

1 patent

MICRON TECHNOLOGY INC

1 patent

SODANI AVINASH

1 patent

AMPERE COMPUTING LLC

1 patent