Inventor

RONEN RONNY

IL86 patents

⚠️ This page may combine multiple inventors who share the name “RONEN RONNY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RONEN RONNY

INTEL CORP

Distribution of processing activity across processing hardware based on power consumption considerations

Instruction segment recording scheme

Distribution of processing activity in a multiple core microprocessor

Low-power processor hint, such as from a PAUSE instruction

Register renaming to optimize identical register values

Correlated address prediction

Method and apparatus for varying energy per instruction according to the amount of available parallelism

System and method for early resolution of low confidence branches and safe data cache accesses

Method and system for branch target prediction using path information

Method and apparatus for cache line prediction and prefetching using a prefetch controller and buffer and access history

System and method for fusing instructions

Unified renaming scheme for load and store instructions

Mapping destination logical register to physical register storing immediate or renamed source register of move instruction and using mapping counters

Cache structure for storing variable length data

Method and apparatus for predicting when load instructions can be executed out-of order

Method and apparatus for providing a re-ordered instruction cache in a pipelined microprocessor

Method and apparatus for executing a 32-bit application by confining the application to a 32-bit address space subset in a 64-bit processor

Prediction of issued silent store operations for allowing subsequently issued loads to bypass unexecuted silent stores and confirming the bypass upon execution of the stores

Cache structure for storing variable length data

Controlling population size of confidence assignments

Method of modifying an instruction set architecture of a computer processor to maintain backward compatibility

Combining power prediction and optimal control approaches for performance optimization in thermally limited designs

System and method for fusing instructions

Methods and apparatus for optimal voltage and frequency control of thermally limited systems

Deterministic power-estimation for thermal control

Generating lookahead tracked register value based on arithmetic operation indication

Power reduction for processor front-end by caching decoded instructions

System, apparatus and method for prioritizing instructions and eliminating useless instructions

Cache memory bank access prediction

Enhanced virtual renaming scheme and deadlock prevention therefor

Method and system for safe data dependency collapsing based on control-flow speculation

Method for optimized representation of page table entries

Out-of-order superscalar microprocessor with a renaming device that maps instructions from memory to registers

Fast branch misprediction recovery method and system

Method and apparatus for a register renaming structure

Methods and apparatus for optimal voltage and frequency control of thermally limited systems

Apparatus and method for accelerating operations in a processor which uses shared virtual memory

Method and apparatus to vectorize multiple input instructions

Method and apparatus for optimizing load memory accesses

Lookahead register value tracking

Memory record update filtering

Selectively protecting a register file

Trace cache filtering

FINKELSTEIN LEV

Method for optimizing voltage-frequency setup in multi-core processor systems

Power management for multiple processor cores

GINZBURG BORIS

Context switching mechanism for a processing core having a general purpose CPU core and a tightly coupled accelerator

Providing an asymmetric multicore processor system transparently to an operating system

RONEN RONNY

Compiler-directed sign/zero extension of a first bit size result to overwrite incorrect data before subsequent processing involving the result within an architecture supporting larger second bit size values

WEISSMANN ELIEZER

Apparatus and method for accelerating operations in a processor which uses shared virtual memory

SHEAFFER GAD

Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform