Inventor

AZADET KAMERAN

US127 patents

⚠️ This page may combine multiple inventors who share the name “AZADET KAMERAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AZADET KAMERAN

INTEL CORP

Non-linear modeling of a physical system using look-up table with polynomial interpolation

Wireless communication technology, apparatuses, and methods

Non-linear interference cancellation for wireless transceivers

Apparatus and method for analog-to-digital conversion

Wireless communication technology, apparatuses, and methods

Digital-to-analog converter

Modeling of a physical system using two-dimensional look-up table and linear interpolation

Modeling of a target volterra series using an orthogonal parallel wiener decomposition

Digital predistortion for dual-band power amplifiers

Non-linear modeling of a physical system using direct optimization of look-up table values

Vector processor having instruction set with sliding window non-linear convolutional function

Software digital front end (SoftDFE) signal processing

Maximum likelihood bit-stream generation and detection using M-algorithm and infinite impulse response filtering

System and method for calibrating a time-interleaved digital-to-analog converter

Segmented digital-to-analog converter with subtractive dither

Direct digital synthesis of signals using maximum likelihood bit-stream encoding

Digital-to-analog converter, transmitter, base station and mobile device

n-bit successive approximation register analog-to-digital converter and method for calibrating the same, receiver, base station and mobile device

Digital-to-analog conversion system

Arbitrary noise shaping transmitter with receive band notches

Devices and methods for pyramid stream encoding

Apparatus for generating a plurality of phase-shifted clock signals, electronic system, base station and mobile device

AGERE SYSTEMS INC

Digital phase-looked loop

Method and apparatus for power management using transmission mode with reduced power

Pulse amplitude modulated transmission scheme for optical channels with soft decision decoding

Method and apparatus for pipelined joint equalization and decoding for gigabit communications

Method and apparatus for converting between analog and digital domains using frequency interleaving

Methods and apparatus for improved phase linearity in a multi-phase based clock/timing recovery system

Method and apparatus for reducing cross-talk with reduced redundancies

Mixed-mode next/echo canceller for pulse amplitude modulated (PAM) signals

Methods and apparatus for interface adapter integrated virus protection

Method and apparatus for joint equalization and decoding of multilevel codes

Method and apparatus for pipelined joint equalization and decoding for gigabit communications

Method and apparatus for cross-talk cancellation in frequency division multiplexed transmission systems

Programmable receive-side channel equalizer

LUCENT TECHNOLOGIES INC

Parallel processing decision-feedback equalizer (DFE) with look-ahead processing

Method and apparatus for shortening the critical path of reduced complexity sequence estimation techniques

Zero-latency pipeline architecture for digital filters

Second order LMS tap update algorithm with high tracking capability

Voltage comparator requiring no compensating offset voltage

LSI CORP

Crest factor reduction (CFR) using asymmetrical pulses

Recursive digital pre-distortion (DPD)

Block-based crest factor reduction (CFR)

BiCMOS gate driver for class-S radio frequency power amplifier

Methods and apparatus for whitening quantization noise in a delta-sigma modulator using dither signal

AZADET KAMERAN

Digital signal processor having instruction set with an xK function using reduced look-up table

Receiver and method for estimating a plurality of estimated transfer functions corresponding to wireless channels in a multiple-input system

Digital signal processor having instruction set with a logarithm function using reduced look-up table

Digital signal processor having instruction set with one or more non-linear functions using reduced look-up table with exponentially varying step-size

AGERE SYST GUARDIAN CORP

Parallel processing decision feedback equalizer