Inventor

HARATSCH ERICH F

US159 patents

⚠️ This page may combine multiple inventors who share the name “HARATSCH ERICH F”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HARATSCH ERICH F

SEAGATE TECHNOLOGY LLC

Internal copy-back with read-verify

Read retry operations where likelihood value assignments change sign at different read voltages for each read retry

Read retry operations with read reference voltages ranked for different page populations of a memory

Adaptive read threshold voltage tracking with charge leakage mitigation using threshold voltage offsets

Mitigation of error correction failure due to trapping sets

Read retry operations with estimation of written data based on syndrome weights

Read retry for non-volatile memories

Reduced polar codes

Adaptive read threshold voltage tracking with bit error rate estimation based on non-linear syndrome weight mapping

Independent read threshold voltage tracking for multiple dependent read threshold voltages using syndrome weights

Flash memory read error recovery with soft-decision decode

Establishing parameters of subsequent read retry operations based on syndrome weights of prior failed decodings

Systems and methods for soft decision generation in a solid state memory system

Framework for balancing robustness and latency during collection of statistics from soft reads

Reduction or elimination of a latency penalty associated with adjusting read thresholds for non-volatile memory

Systems and methods for dynamically programming a flash memory device

Write mapping to mitigate hard errors via soft-decision decoding

Cell-level statistics collection for detection and decoding in flash memories

Bad memory unit detection in a solid state drive

Estimating read reference voltage based on disparity and derivative metrics

Error correction code (ECC) selection using probability density functions of error correction capability in storage controllers with multiple error correction codes

Adjusting log likelihood ratio values to compensate misplacement of read voltages

Systems and methods for differential message scaling in a decoding process

Recovery strategy that reduces errors misidentified as reliable

Log-likelihood ratio (LLR) dampening in low-density parity-check (LDPC) decoders

Method to dynamically update LLRs in an SSD drive and/or controller

Mitigation of write errors in multi-level cell flash memory through adaptive error correction code decoding

Soft decoding of polar codes

Method to distribute user data and error correction data over different page types by leveraging error rate variations

Multiple retry reads in a read channel of a memory

Write mapping to mitigate hard errors via soft-decision decoding

Reduced polar codes

Systems and methods for soft data utilization in a solid state memory system

Flash channel with selective decoder likelihood dampening

Policy for read operations addressing on-the-fly decoding failure in non-volatile memory

LSI CORP

Systems and methods for track to track phase alignment

Flash memory read retry using histograms

Method and apparatus for generation of soft decision error correction code information

Flash memory read error recovery with soft-decision decode

Compensation loop for read voltage adaptation

HARATSCH ERICH F

Methods and apparatus for computing soft data or log likelihood ratios for received values in communication or storage systems

Methods and apparatus for approximating a probability density function or distribution for a received value in communication or storage systems

Methods and apparatus for read-side intercell interference mitigation in flash memories

Methods and apparatus for soft demapping and intercell interference mitigation in flash memories

AGERE SYSTEMS INC

Systems and methods for generating erasure flags

Systems and methods for prioritizing error correction data

BURGER JR HARLEY F

Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding

AVAGO TECHNOLOGIES GENERAL IP

Systems and methods for dynamically programming a flash memory device

MATHEW GEORGE

Systems and methods for inter-track interference compensation

GRAEF NILS

Methods and apparatus for intercell interference mitigation using modulation coding