Inventor

FLACHOWSKY STEFAN

DE109 patents

⚠️ This page may combine multiple inventors who share the name “FLACHOWSKY STEFAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FLACHOWSKY STEFAN

GLOBALFOUNDRIES INC

Integrated circuits with fets having nanowires and methods of manufacturing the same

Method of forming a device including a floating gate electrode and a layer of ferroelectric material

Ferroelectric FinFET

Multi-gate FETs having corrugated semiconductor stacks and method of forming the same

Channel SiGe removal from PFET source/drain region for improved silicide formation in HKMG technologies without embedded SiGe

Source and drain doping using doped raised source and drain regions

E-fuse design for high-K metal-gate technology

Transistor with embedded stress-inducing layers

Semiconductor structure including a first transistor and a second transistor

Temperature independent resistor

Simplified gate-first HKMG manufacturing flow

Contact geometry having a gate silicon length decoupled from a transistor length

Semiconductor device structure and methods for forming a CMOS integrated circuit structure

Method of forming a semiconductor structure including a vertical nanowire

Forming transistors without spacers and resulting devices

Method of forming a semiconductor device structure and such a semiconductor device structure

Three-dimensional transistor with improved channel mobility

Methods of removing gate cap layers in CMOS applications

Method for forming a semiconductor device and semiconductor device structures

Full silicidation prevention via dual nickel deposition approach

Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof

Integrated circuits and methods for operating integrated circuits with non-volatile memory

FLACHOWSKY STEFAN

Replacement gate FinFET structures with high mobility channel

In situ doping and diffusionless annealing of embedded stressor regions in PMOS and NMOS devices

Methods of performing highly tilted halo implantation processes on semiconductor devices

Method of increasing the germanium concentration in a silicon-germanium layer and semiconductor device comprising same

Semiconductor device with strain-inducing regions and method thereof

Integrated circuits formed on strained substrates and including relaxed buffer layers and methods for the manufacture thereof

Transistor comprising an embedded sigma shaped sequentially formed semiconductor alloy

Methods for the fabrication of integrated circuits including back-etching of raised conductive structures

Methods of forming stressed silicon-carbon areas in an NMOS transistor

Drive current increase in field effect transistors by asymmetric concentration profile of alloy species of a channel semiconductor alloy

Stress enhanced CMOS circuits and methods for their manufacture

Performance enhancement in transistors by reducing the recessing of active regions and removing spacers

Semiconductor device with strain-inducing regions and method thereof

Canyon gate transistor and methods for its fabrication

Methods for fabricating MOS devices with stress memorization

Methods of forming semiconductor devices with embedded semiconductor material as source/drain regions using a reduced number of spacers

HOENTSCHEL JAN

Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

Strain transformation in biaxially strained SOI substrates for performance enhancement of P-channel and N-channel transistors

SCHEIPER THILO

Methods for fabricating integrated circuits having gate to active and gate to gate interconnects

Semiconductor device with dual metal silicide regions and methods of making same

Sacrificial spacer approach for differential source/drain implantation spacers in transistors comprising a high-k metal gate electrode structure

GLOBALFOUNDRIES SG PTE LTD

Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

BALDAUF TIM

Integrated circuits having protruding source and drain regions and methods for forming integrated circuits

FRAUNHOFER GES FORSCHUNG

Device including a floating gate electrode and a layer of ferroelectric material and method for the formation thereof

GERHARDT MARTIN

Methods of forming transistor devices with high-k insulation layers and the resulting devices

ILLGEN RALF

Ultrathin body fully depleted silicon-on-insulator integrated circuits and methods for fabricating same

JAVORKA PETER

Full silicidation prevention via dual nickel deposition approach