Inventor

HOENTSCHEL JAN

DE174 patents

⚠️ This page may combine multiple inventors who share the name “HOENTSCHEL JAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOENTSCHEL JAN

GLOBALFOUNDRIES INC

Integrated circuits with fets having nanowires and methods of manufacturing the same

Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same

Integrated circuit including a dummy gate structure and method for the formation thereof

Wafer with SOI structure having a buried insulating multilayer structure and semiconductor device structure

Ferroelectric FinFET

Multi-gate FETs having corrugated semiconductor stacks and method of forming the same

Method of forming a semiconductor device and resulting semiconductor devices

Channel SiGe removal from PFET source/drain region for improved silicide formation in HKMG technologies without embedded SiGe

Source and drain doping using doped raised source and drain regions

Method of forming a semiconductor structure including an implantation of ions into a layer of spacer material

Work function adjustment in high-k gate stacks for devices of different threshold voltage

Transistor including a high-K metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacer

Method for reducing crystal defects in transistors with re-grown shallow junctions by appropriately selecting crystalline orientations

Transistor with embedded stress-inducing layers

BULEX contacts in advanced FDSOI techniques

ADVANCED MICRO DEVICES INC

Drive current increase in transistors by asymmetric amorphization implantation

Different embedded strain layers in PMOS and NMOS transistors and a method of forming the same

Embedded strain layer in thin SOI transistors and a method of forming the same

Technique for providing multiple stress sources in NMOS and PMOS transistors

Semiconductor structure comprising field effect transistors with stressed channel regions and method of forming the same

Technique for forming recessed strained drain/source regions in NMOS and PMOS transistors

SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device

SOI transistor having an embedded strain layer and a reduced floating body effect and a method for forming the same

Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions

Technique for forming a strained transistor by a late amorphization and disposable spacers

SOI transistor having a reduced body potential and a method of forming the same

FLACHOWSKY STEFAN

Replacement gate FinFET structures with high mobility channel

Methods of performing highly tilted halo implantation processes on semiconductor devices

Method of increasing the germanium concentration in a silicon-germanium layer and semiconductor device comprising same

Semiconductor device with strain-inducing regions and method thereof

Integrated circuits formed on strained substrates and including relaxed buffer layers and methods for the manufacture thereof

Transistor comprising an embedded sigma shaped sequentially formed semiconductor alloy

Methods for the fabrication of integrated circuits including back-etching of raised conductive structures

HOENTSCHEL JAN

Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

Strain engineering in three-dimensional transistors based on globally strained semiconductor base layers

Asymmetric transistor devices formed by asymmetric spacers and tilted implantation

Asymmetric transistor devices formed by asymmetric spacers and tilted implantation

Adjusting configuration of a multiple gate transistor by controlling individual fins

Performance enhancement in PMOS and NMOS transistors on the basis of silicon/carbon material

BEYER SVEN

Multiple gate transistor having homogenously silicided fin end portions

Transistors comprising high-k metal gate electrode structures and adapted channel semiconductor materials

GRIEBENOW UWE

Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage

Increased depth of drain and source regions in complementary transistors by forming a deep drain and source region prior to a cavity etch

SCHEIPER THILO

Replacement gate approach based on a reverse offset spacer applied prior to work function metal deposition

Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement

GLOBALFOUNDRIES SG PTE LTD

Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

WEI ANDY

Contact trenches for enhancing stress transfer in closely spaced transistors

MULFINGER ROBERT

Transistor with embedded SI/GE material having enhanced across-substrate uniformity

PAPAGEORGIOU VASSILIOS

Transistor device comprising an asymmetric embedded semiconductor alloy