Inventor

NGUYEN BICH-YEN

US134 patents

⚠️ This page may combine multiple inventors who share the name “NGUYEN BICH-YEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NGUYEN BICH-YEN

MOTOROLA INC

Memory device that includes passivated nanoclusters and method for manufacture

Memory device and method for using prefabricated isolated storage elements

Method for forming a semiconductor device with an opening in a dielectric layer

Process for forming a high-K gate dielectric

Method for forming pitch independent contacts and a semiconductor device having the same

Strontium nitride or strontium oxynitride gate dielectric

Dual metal gate transistors for CMOS process

Process for forming high purity thin films

High K dielectric film

Semiconductor device and a method therefor

Memory device and method for manufacture

Method for forming contact to a semiconductor device

Method and structure for forming an integrated circuit pattern on a semiconductor substrate

Method for forming a thin film transistor

Interconnection structure for conductive layers

Method and structure for forming an integrated circuit pattern on a semiconductor substrate

Method for forming an interconnection structure for conductive layers

Integrated circuit trench cell

Method of making a power switching trench MOSFET having aligned source regions

Method for locos isolation using a framed oxidation mask and a polysilicon buffer layer

Method for forming an integrated circuit pattern on a semiconductor substrate using silicon-rich silicon nitride

Method of removing contaminants

Trench formation process

Dual metal gate transistors for CMOS process

High-performance thin-film transistor and SRAM memory cell

Thin film transistor and method of formation

Thin film transistor having a self-aligned gate underlying a channel region

Semiconductor structure and process for forming a metal oxy-nitride dielectric layer

FREESCALE SEMICONDUCTOR INC

Semiconductor device structure and method therefor

Method for forming a double-gated semiconductor device

Inverse slope isolation and dual surface orientation integration

Method of making a dual strained channel semiconductor device

Method for forming a semiconductor device having a strained channel and a heterojunction source/drain

Semiconductor structure with different lattice constant materials and method for forming the same

Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor

High K dielectric film

Asymmetric spacers and asymmetric source/drain extension layers

Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer

Modified hybrid orientation technology

Method of forming a CMOS device with stressor source/drain regions

Transistor fabrication using double etch/refill process

Low RC product transistors in SOI semiconductor process

Template layer formation

Semiconductor fabrication process including recessed source/drain regions in an SOI wafer

Double gate device having a heterojunction source/drain and strained channel

Method of manufacturing SOI template layer

Semiconductor transistor having structural elements of differing materials and method of formation

Dual metal gate transistors for CMOS process

Confined spacers for double gate transistor semiconductor fabrication process

NGUYEN BICH-YEN

Methods of forming three dimensionally integrated semiconductor systems including photoactive devices and semiconductor-on-insulator substrates