Inventor
KOCH GARRETT S
US10 patents
Patents
10 patentsUS6430073B1Aug 6, 2002
Dram CAM cell with hidden refresh
IBM95 citations97
US5796745AAug 18, 1998
Memory array built-in self test circuit for testing multi-port memory arrays
IBM105 citations97
US5535164AJul 9, 1996
BIST tester for multiple memories
IBM149 citations96
US7003704B2Feb 21, 2006
Two-dimensional redundancy calculation
IBM20 citations92
US5563833AOct 8, 1996
Using one memory to supply addresses to an associated memory during testing
IBM23 citations92
US5317573AMay 31, 1994
Apparatus and method for real time data error capture and compression redundancy analysis
IBM44 citations88
US6282144B1Aug 28, 2001
Multi-ported memory with asynchronous and synchronous protocol
IBM14 citations73
US7117400B2Oct 3, 2006
Memory device with data line steering and bitline redundancy
IBM5 citations62
US5093584AMar 3, 1992
Self calibrating timing circuit
IBM4 citations58
US7562267B2Jul 14, 2009
Methods and apparatus for testing a memory
IBM0 citations48