Inventor

MAHURIN ERIC W

US27 patents

⚠️ This page may combine multiple inventors who share the name “MAHURIN ERIC W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MAHURIN ERIC W

ADVANCED MICRO DEVICES INC

Instruction decode unit producing instruction operand information in the order in which the operands are identified, and systems including same

Merging narrow register for resolution of data dependencies when updating a portion of a register in a microprocessor

Detecting full conditions in a queue

Method and circuit for determining leading or trailing zero count

Circuit for shifting or rotating operands of multiple size

Integrated circuit design with cell-based macros

Programming paradigm and microprocessor architecture for exact branch targeting

Circuit for parity tree structure

Shared dependency checking for status flags

Method and circuit for detecting overflow in operand multiplication

Method and apparatus for performing overshifted rotate through carry instructions by shifting in opposite directions

Circuit and method for determining overflow in signed division

Circuit and method employing an adder for sign extending operands

Circuit and method for shifting or rotating operands of multiple size

Method and circuitry for an undisturbed scannable state element

Method and circuit for performing a shift arithmetic right operation

Combined add/shift structure

Combination propagate and generate carry lookahead gate

Method and circuit for adding operands of multiple size

INTEL CORP

Processor to perform a bit range isolation instruction

Processor to perform a bit range isolation instruction

System-on-chip (SoC) to perform a bit range isolation instruction

Hand held device to perform a bit range isolation instruction

CHOU YUAN C

Reducing power consumption and resource utilization during miss lookahead

Prefetching load data in lookahead mode and invalidating architectural registers instead of writing results for retiring instructions

WIEDEMEIER JEFF

Functional unit for vector leading zeroes, vector trailing zeroes, vector operand 1s count and vector parity calculation

LOKTYUKHIN MAXIM

Bit range isolation instructions, methods, and apparatus