Inventor

CHO UK-RAE

KR49 patents

⚠️ This page may combine multiple inventors who share the name “CHO UK-RAE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHO UK-RAE

SAMSUNG ELECTRONICS CO LTD

Impedance control circuit

Programmable impedance control circuit

Programmable impedance control circuit

Programmable termination circuit and method

Method and apparatus for controlling impedance of an off-chip driver circuit

Semiconductor device with programmable impedance control circuit

Semiconductor memory device with hierarchical bit line structure

Semiconductor device with impedance control circuit

Programmable impedance control circuit and method thereof

Memory architecture permitting selection of storage density after fabrication of active circuitry

Integrated circuit chips and wafers including on-chip test element group circuits, and methods of fabricating and testing same

Circuits and methods for screening for defective memory cells in semiconductor memory devices

Stacked memory cell for use in high-density CMOS SRAM

Delay-locked loop circuits and method for generating transmission core clock signals

Semiconductor memory device with hierarchical bit line structure

Method and circuit for writing double data rate (DDR) sampled data in a memory device

Impedance controller and impedance control method

Semiconductor memory device capable of generating variable clock signals according to modes of operation

Circuits and methods for generating internal clock signal of intermediate phase relative to external clock

Signal converting system having level converter for use in high speed semiconductor device and method therefor

Impedance updating apparatus of termination circuit and impedance updating method thereof

Semiconductor device and method of fabricating the same

Content addressable memory device

Semiconductor memory device capable of performing high-frequency wafer test operation

Phase interpolation circuit and method of generating phase interpolation signal

Integrated circuit with on-chip termination

Data line layout and line driving method in semiconductor memory device

Semiconductor memory device with hierarchical bit line structure

Semiconductor memory device testable with a single data rate and/or dual data rate pattern in a merged data input/output pin test mode

Apparatus for generating internal clock signal

Synchronous mirror delay circuit and semiconductor integrated circuit device having the same

Internal clock generating circuit of semiconductor memory device and method thereof

Gunn transceiver logic input circuit for use in a semiconductor memory device

Impedance control circuit in semiconductor device and impedance control method

Impedance controllable ouput drive circuit in semiconductor device and impedance control method therefor

BiCMOS semiconductor device

Method of fabricating a semiconductor device

Semiconductor devices

Method for making a BiCMOS semiconductor device

Amplifier circuit having constant output swing range and stable delay time

Amplifier circuit having constant output swing range and stable delay time

Content addressable memory device

Control signal transmitting method with package power pin and related integrated circuit package structure

Semiconductor device and method for operating the same

Semiconductor device and method for operating the same

Output impedance circuit and output buffer circuit including the same

SAMSUNG ELECTRONICS LTD

Layout structure of MOS transistors on an active region

JUNG GUN OK

Flip-flop and semiconductor device including the same

SON YOUNG-JAE

Delay test device and system-on-chip having the same