P

Inventor

SAKALLAH KAREM A

US7 patents
⚠️ This page may combine multiple inventors who share the name “SAKALLAH KAREM A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CADENCE DESIGN SYSTEMS INC

4 patents
US6457159B1Sep 24, 2002

Functional timing analysis for characterization of virtual component blocks

CADENCE DESIGN SYSTEMS INC30 citations91
US6442739B1Aug 27, 2002

System and method for timing abstraction of digital logic circuits

CADENCE DESIGN SYSTEMS INC42 citations90
US6877143B1Apr 5, 2005

System and method for timing abstraction of digital logic circuits

CADENCE DESIGN SYSTEMS INC6 citations71
US7346872B2Mar 18, 2008

Functional timing analysis for characterization of virtual component blocks

CADENCE DESIGN SYSTEMS INC1 citations47

UNIV MICHIGAN

1 patent
US8954909B2Feb 10, 2015

Automated scalable verification for hardware designs at the register transfer level

UNIV MICHIGAN6 citations79

ANDRAUS ZAHER

1 patent
US8601414B2Dec 3, 2013

Automated scalable verification for hardware designs at the register transfer level

ANDRAUS ZAHER8 citations74

SAKALLAH KAREM A

1 patent
US9389983B2Jul 12, 2016

Verification of complex systems that can be described by a finite state transition system

SAKALLAH KAREM A1 citations43